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git01.mediatek.com / filogic / uboot / 131c3322149561b398fd0ae4a7eaabcbc30898ee / . / drivers / clk / sunxi / clk_h3.c
blob: f81633b92d5a3426bb52733f0a85b9ddbdc67b21 [file] [log] [blame]
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun8i-h3-ccu.h>
13#include <dt-bindings/reset/sun8i-h3-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]15
16static struct ccu_clk_gate h3_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]20 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]21 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]23 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
24 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
25 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
26 [CLK_BUS_EHCI2] = GATE(0x060, BIT(26)),
27 [CLK_BUS_EHCI3] = GATE(0x060, BIT(27)),
28 [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
29 [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
30 [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
31 [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
32
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]33 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
34 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
35 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
36 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
37
Jagan Teki755e1812019-02-28 00:26:59 +0530[diff] [blame]38 [CLK_BUS_EPHY] = GATE(0x070, BIT(0)),
39
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]40 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
41 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
42
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]43 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
44 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
45 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
46 [CLK_USB_PHY3] = GATE(0x0cc, BIT(11)),
47 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
48 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
49 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
50 [CLK_USB_OHCI3] = GATE(0x0cc, BIT(19)),
51};
52
53static struct ccu_reset h3_resets[] = {
54 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
55 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
56 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
57 [RST_USB_PHY3] = RESET(0x0cc, BIT(3)),
58
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]59 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
60 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
61 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]62 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]63 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
64 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]65 [RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
66 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
67 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
68 [RST_BUS_EHCI2] = RESET(0x2c0, BIT(26)),
69 [RST_BUS_EHCI3] = RESET(0x2c0, BIT(27)),
70 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
71 [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
72 [RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)),
73 [RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]74
Jagan Teki755e1812019-02-28 00:26:59 +0530[diff] [blame]75 [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)),
76
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]77 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
78 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
79 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
80 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]81};
82
83static const struct ccu_desc h3_ccu_desc = {
84 .gates = h3_gates,
85 .resets = h3_resets,
86};
87
88static int h3_clk_bind(struct udevice *dev)
89{
90 return sunxi_reset_bind(dev, ARRAY_SIZE(h3_resets));
91}
92
93static const struct udevice_id h3_ccu_ids[] = {
94 { .compatible = "allwinner,sun8i-h3-ccu",
95 .data = (ulong)&h3_ccu_desc },
96 { .compatible = "allwinner,sun50i-h5-ccu",
97 .data = (ulong)&h3_ccu_desc },
98 { }
99};
100
101U_BOOT_DRIVER(clk_sun8i_h3) = {
102 .name = "sun8i_h3_ccu",
103 .id = UCLASS_CLK,
104 .of_match = h3_ccu_ids,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700[diff] [blame]105 .priv_auto = sizeof(struct ccu_priv),
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]106 .ops = &sunxi_clk_ops,
107 .probe = sunxi_clk_probe,
108 .bind = h3_clk_bind,
109};