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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Vikas Manocha5dba05e2016-02-11 15:47:19 -08002/*
Patrice Chotard789ee0e2017-10-23 09:53:58 +02003 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
Vikas Manocha5dba05e2016-02-11 15:47:19 -08005 */
6
7#include <common.h>
Vikas Manocha7b00ff92017-02-12 10:25:46 -08008#include <clk.h>
Vikas Manocha5dba05e2016-02-11 15:47:19 -08009#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Patrice Chotard4d6701e2018-12-04 14:11:36 +010011#include <reset.h>
Vikas Manocha5dba05e2016-02-11 15:47:19 -080012#include <serial.h>
Patrick Delaunayab8e5d22018-05-17 14:50:42 +020013#include <watchdog.h>
14#include <asm/io.h>
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +090015#include <asm/arch/stm32.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060016#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060017#include <linux/delay.h>
Patrice Chotard9e276502018-01-12 09:23:49 +010018#include "serial_stm32.h"
Simon Glass9bc15642020-02-03 07:36:16 -070019#include <dm/device_compat.h>
Vikas Manocha5dba05e2016-02-11 15:47:19 -080020
Patrick Delaunayab8e5d22018-05-17 14:50:42 +020021static void _stm32_serial_setbrg(fdt_addr_t base,
22 struct stm32_uart_info *uart_info,
23 u32 clock_rate,
24 int baudrate)
Vikas Manocha5dba05e2016-02-11 15:47:19 -080025{
Patrick Delaunayab8e5d22018-05-17 14:50:42 +020026 bool stm32f4 = uart_info->stm32f4;
Patrice Chotard4809a192017-07-18 09:29:08 +020027 u32 int_div, mantissa, fraction, oversampling;
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +090028
Patrick Delaunayab8e5d22018-05-17 14:50:42 +020029 int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate);
Patrice Chotard31496322017-06-08 09:26:55 +020030
31 if (int_div < 16) {
32 oversampling = 8;
Patrice Chotard5011e6f2017-09-27 15:44:50 +020033 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
Patrice Chotard31496322017-06-08 09:26:55 +020034 } else {
35 oversampling = 16;
Patrice Chotard5011e6f2017-09-27 15:44:50 +020036 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
Patrice Chotard31496322017-06-08 09:26:55 +020037 }
38
39 mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
40 fraction = int_div % oversampling;
41
Patrice Chotard5011e6f2017-09-27 15:44:50 +020042 writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
Patrick Delaunayab8e5d22018-05-17 14:50:42 +020043}
44
45static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
46{
Simon Glassb75b15b2020-12-03 16:55:23 -070047 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
Patrick Delaunayab8e5d22018-05-17 14:50:42 +020048
49 _stm32_serial_setbrg(plat->base, plat->uart_info,
50 plat->clock_rate, baudrate);
Vikas Manocha5dba05e2016-02-11 15:47:19 -080051
52 return 0;
53}
54
Patrice Chotard34e64c02018-08-03 15:07:39 +020055static int stm32_serial_setconfig(struct udevice *dev, uint serial_config)
Patrick Delaunay39ffe0e2018-05-17 14:50:45 +020056{
Simon Glassb75b15b2020-12-03 16:55:23 -070057 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
Patrick Delaunay39ffe0e2018-05-17 14:50:45 +020058 bool stm32f4 = plat->uart_info->stm32f4;
59 u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
60 u32 cr1 = plat->base + CR1_OFFSET(stm32f4);
61 u32 config = 0;
Patrice Chotard34e64c02018-08-03 15:07:39 +020062 uint parity = SERIAL_GET_PARITY(serial_config);
63 uint bits = SERIAL_GET_BITS(serial_config);
64 uint stop = SERIAL_GET_STOP(serial_config);
Patrick Delaunay39ffe0e2018-05-17 14:50:45 +020065
Patrice Chotard34e64c02018-08-03 15:07:39 +020066 /*
67 * only parity config is implemented, check if other serial settings
68 * are the default one.
69 * (STM32F4 serial IP didn't support parity setting)
70 */
71 if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP || stm32f4)
72 return -ENOTSUPP; /* not supported in driver*/
Patrick Delaunay39ffe0e2018-05-17 14:50:45 +020073
74 clrbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
75 /* update usart configuration (uart need to be disable)
Patrice Chotard34e64c02018-08-03 15:07:39 +020076 * PCE: parity check enable
Patrick Delaunay39ffe0e2018-05-17 14:50:45 +020077 * PS : '0' : Even / '1' : Odd
78 * M[1:0] = '00' : 8 Data bits
79 * M[1:0] = '01' : 9 Data bits with parity
80 */
81 switch (parity) {
82 default:
83 case SERIAL_PAR_NONE:
84 config = 0;
85 break;
86 case SERIAL_PAR_ODD:
87 config = USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0;
88 break;
89 case SERIAL_PAR_EVEN:
90 config = USART_CR1_PCE | USART_CR1_M0;
91 break;
92 }
Patrice Chotard34e64c02018-08-03 15:07:39 +020093
Patrick Delaunay39ffe0e2018-05-17 14:50:45 +020094 clrsetbits_le32(cr1,
95 USART_CR1_PCE | USART_CR1_PS | USART_CR1_M1 |
96 USART_CR1_M0,
97 config);
98 setbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
99
100 return 0;
101}
102
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800103static int stm32_serial_getc(struct udevice *dev)
104{
Simon Glassb75b15b2020-12-03 16:55:23 -0700105 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
Patrice Chotard5011e6f2017-09-27 15:44:50 +0200106 bool stm32f4 = plat->uart_info->stm32f4;
107 fdt_addr_t base = plat->base;
Patrice Chotard24af24b2018-04-20 08:59:06 +0200108 u32 isr = readl(base + ISR_OFFSET(stm32f4));
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800109
Patrice Chotarddb0536e2018-05-17 14:50:43 +0200110 if ((isr & USART_ISR_RXNE) == 0)
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800111 return -EAGAIN;
112
Patrick Delaunay1a103bf2019-07-30 19:16:46 +0200113 if (isr & (USART_ISR_PE | USART_ISR_ORE | USART_ISR_FE)) {
Patrice Chotard24af24b2018-04-20 08:59:06 +0200114 if (!stm32f4)
Patrick Delaunay39ffe0e2018-05-17 14:50:45 +0200115 setbits_le32(base + ICR_OFFSET,
Patrick Delaunay1a103bf2019-07-30 19:16:46 +0200116 USART_ICR_PCECF | USART_ICR_ORECF |
117 USART_ICR_FECF);
Patrice Chotard24af24b2018-04-20 08:59:06 +0200118 else
119 readl(base + RDR_OFFSET(stm32f4));
120 return -EIO;
121 }
122
Patrice Chotard5011e6f2017-09-27 15:44:50 +0200123 return readl(base + RDR_OFFSET(stm32f4));
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800124}
125
Patrick Delaunayab8e5d22018-05-17 14:50:42 +0200126static int _stm32_serial_putc(fdt_addr_t base,
127 struct stm32_uart_info *uart_info,
128 const char c)
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800129{
Patrick Delaunayab8e5d22018-05-17 14:50:42 +0200130 bool stm32f4 = uart_info->stm32f4;
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800131
Patrice Chotarddb0536e2018-05-17 14:50:43 +0200132 if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_TXE) == 0)
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800133 return -EAGAIN;
134
Patrice Chotard5011e6f2017-09-27 15:44:50 +0200135 writel(c, base + TDR_OFFSET(stm32f4));
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800136
137 return 0;
138}
139
Patrick Delaunayab8e5d22018-05-17 14:50:42 +0200140static int stm32_serial_putc(struct udevice *dev, const char c)
141{
Simon Glassb75b15b2020-12-03 16:55:23 -0700142 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
Patrick Delaunayab8e5d22018-05-17 14:50:42 +0200143
144 return _stm32_serial_putc(plat->base, plat->uart_info, c);
145}
146
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800147static int stm32_serial_pending(struct udevice *dev, bool input)
148{
Simon Glassb75b15b2020-12-03 16:55:23 -0700149 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
Patrice Chotard5011e6f2017-09-27 15:44:50 +0200150 bool stm32f4 = plat->uart_info->stm32f4;
151 fdt_addr_t base = plat->base;
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800152
153 if (input)
Patrice Chotard5011e6f2017-09-27 15:44:50 +0200154 return readl(base + ISR_OFFSET(stm32f4)) &
Patrice Chotarddb0536e2018-05-17 14:50:43 +0200155 USART_ISR_RXNE ? 1 : 0;
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800156 else
Patrice Chotard5011e6f2017-09-27 15:44:50 +0200157 return readl(base + ISR_OFFSET(stm32f4)) &
Patrice Chotarddb0536e2018-05-17 14:50:43 +0200158 USART_ISR_TXE ? 0 : 1;
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800159}
160
Patrick Delaunayab8e5d22018-05-17 14:50:42 +0200161static void _stm32_serial_init(fdt_addr_t base,
162 struct stm32_uart_info *uart_info)
163{
164 bool stm32f4 = uart_info->stm32f4;
165 u8 uart_enable_bit = uart_info->uart_enable_bit;
166
167 /* Disable uart-> enable fifo -> enable uart */
168 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
169 BIT(uart_enable_bit));
170 if (uart_info->has_fifo)
171 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
172 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
173 BIT(uart_enable_bit));
174}
175
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800176static int stm32_serial_probe(struct udevice *dev)
177{
Simon Glassb75b15b2020-12-03 16:55:23 -0700178 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
Patrice Chotard21aad132017-09-27 15:44:53 +0200179 struct clk clk;
Patrice Chotard4d6701e2018-12-04 14:11:36 +0100180 struct reset_ctl reset;
Patrice Chotard21aad132017-09-27 15:44:53 +0200181 int ret;
Patrice Chotard5011e6f2017-09-27 15:44:50 +0200182
183 plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
Vikas Manocha7b00ff92017-02-12 10:25:46 -0800184
Vikas Manocha7b00ff92017-02-12 10:25:46 -0800185 ret = clk_get_by_index(dev, 0, &clk);
186 if (ret < 0)
187 return ret;
188
189 ret = clk_enable(&clk);
190 if (ret) {
191 dev_err(dev, "failed to enable clock\n");
192 return ret;
193 }
Vikas Manocha7b00ff92017-02-12 10:25:46 -0800194
Patrice Chotard4d6701e2018-12-04 14:11:36 +0100195 ret = reset_get_by_index(dev, 0, &reset);
196 if (!ret) {
197 reset_assert(&reset);
198 udelay(2);
199 reset_deassert(&reset);
200 }
201
Patrice Chotard4809a192017-07-18 09:29:08 +0200202 plat->clock_rate = clk_get_rate(&clk);
Patrick Delaunay3f4afd32019-06-21 15:26:41 +0200203 if (!plat->clock_rate) {
Patrice Chotard4809a192017-07-18 09:29:08 +0200204 clk_disable(&clk);
Patrick Delaunay3f4afd32019-06-21 15:26:41 +0200205 return -EINVAL;
Patrice Chotard4809a192017-07-18 09:29:08 +0200206 };
207
Patrick Delaunayab8e5d22018-05-17 14:50:42 +0200208 _stm32_serial_init(plat->base, plat->uart_info);
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800209
210 return 0;
211}
212
Vikas Manocha19e22c62017-02-12 10:25:44 -0800213static const struct udevice_id stm32_serial_id[] = {
Patrice Chotardb21a69a2017-09-27 15:44:52 +0200214 { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
Patrice Chotard24fc72d2017-09-27 15:44:51 +0200215 { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
216 { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
Vikas Manocha19e22c62017-02-12 10:25:44 -0800217 {}
218};
219
Simon Glassaad29ae2020-12-03 16:55:21 -0700220static int stm32_serial_of_to_plat(struct udevice *dev)
Vikas Manocha19e22c62017-02-12 10:25:44 -0800221{
Simon Glassb75b15b2020-12-03 16:55:23 -0700222 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
Vikas Manocha19e22c62017-02-12 10:25:44 -0800223
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +0900224 plat->base = dev_read_addr(dev);
Patrice Chotard5011e6f2017-09-27 15:44:50 +0200225 if (plat->base == FDT_ADDR_T_NONE)
Vikas Manocha19e22c62017-02-12 10:25:44 -0800226 return -EINVAL;
227
Vikas Manocha19e22c62017-02-12 10:25:44 -0800228 return 0;
229}
Vikas Manocha19e22c62017-02-12 10:25:44 -0800230
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800231static const struct dm_serial_ops stm32_serial_ops = {
232 .putc = stm32_serial_putc,
233 .pending = stm32_serial_pending,
234 .getc = stm32_serial_getc,
235 .setbrg = stm32_serial_setbrg,
Patrice Chotard34e64c02018-08-03 15:07:39 +0200236 .setconfig = stm32_serial_setconfig
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800237};
238
239U_BOOT_DRIVER(serial_stm32) = {
Patrice Chotard9e276502018-01-12 09:23:49 +0100240 .name = "serial_stm32",
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800241 .id = UCLASS_SERIAL,
Vikas Manocha19e22c62017-02-12 10:25:44 -0800242 .of_match = of_match_ptr(stm32_serial_id),
Simon Glassaad29ae2020-12-03 16:55:21 -0700243 .of_to_plat = of_match_ptr(stm32_serial_of_to_plat),
Simon Glassb75b15b2020-12-03 16:55:23 -0700244 .plat_auto = sizeof(struct stm32x7_serial_plat),
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800245 .ops = &stm32_serial_ops,
246 .probe = stm32_serial_probe,
Bin Mengbdb33d82018-10-24 06:36:36 -0700247#if !CONFIG_IS_ENABLED(OF_CONTROL)
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800248 .flags = DM_FLAG_PRE_RELOC,
Bin Mengbdb33d82018-10-24 06:36:36 -0700249#endif
Vikas Manocha5dba05e2016-02-11 15:47:19 -0800250};
Patrick Delaunayab8e5d22018-05-17 14:50:42 +0200251
252#ifdef CONFIG_DEBUG_UART_STM32
253#include <debug_uart.h>
254static inline struct stm32_uart_info *_debug_uart_info(void)
255{
256 struct stm32_uart_info *uart_info;
257
258#if defined(CONFIG_STM32F4)
259 uart_info = &stm32f4_info;
260#elif defined(CONFIG_STM32F7)
261 uart_info = &stm32f7_info;
262#else
263 uart_info = &stm32h7_info;
264#endif
265 return uart_info;
266}
267
268static inline void _debug_uart_init(void)
269{
270 fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
271 struct stm32_uart_info *uart_info = _debug_uart_info();
272
273 _stm32_serial_init(base, uart_info);
274 _stm32_serial_setbrg(base, uart_info,
275 CONFIG_DEBUG_UART_CLOCK,
276 CONFIG_BAUDRATE);
Patrick Delaunayab8e5d22018-05-17 14:50:42 +0200277}
278
279static inline void _debug_uart_putc(int c)
280{
281 fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
282 struct stm32_uart_info *uart_info = _debug_uart_info();
283
284 while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
Patrick Delaunaye093b1c2019-04-18 17:32:51 +0200285 ;
Patrick Delaunayab8e5d22018-05-17 14:50:42 +0200286}
287
288DEBUG_UART_FUNCS
289#endif