| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Vasily Khoruzhick | 37ae5b0 | 2017-09-20 23:29:08 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com> |
| 4 | * Copyright (C) 2017 Vasily Khoruzhick <anarsoul@gmail.com> |
| Vasily Khoruzhick | 37ae5b0 | 2017-09-20 23:29:08 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* Registers at i2c address 0x38 */ |
| 8 | |
| 9 | #define ANX9804_HDCP_CONTROL_0_REG 0x01 |
| 10 | |
| 11 | #define ANX9804_SYS_CTRL1_REG 0x80 |
| 12 | #define ANX9804_SYS_CTRL1_PD_IO 0x80 |
| 13 | #define ANX9804_SYS_CTRL1_PD_VID 0x40 |
| 14 | #define ANX9804_SYS_CTRL1_PD_LINK 0x20 |
| 15 | #define ANX9804_SYS_CTRL1_PD_TOTAL 0x10 |
| 16 | #define ANX9804_SYS_CTRL1_MODE_SEL 0x08 |
| 17 | #define ANX9804_SYS_CTRL1_DET_STA 0x04 |
| 18 | #define ANX9804_SYS_CTRL1_FORCE_DET 0x02 |
| 19 | #define ANX9804_SYS_CTRL1_DET_CTRL 0x01 |
| 20 | |
| 21 | #define ANX9804_SYS_CTRL2_REG 0x81 |
| 22 | #define ANX9804_SYS_CTRL2_CHA_STA 0x04 |
| 23 | |
| 24 | #define ANX9804_SYS_CTRL3_REG 0x82 |
| 25 | #define ANX9804_SYS_CTRL3_VALID_CTRL BIT(0) |
| 26 | #define ANX9804_SYS_CTRL3_F_VALID BIT(1) |
| 27 | #define ANX9804_SYS_CTRL3_HPD_CTRL BIT(4) |
| 28 | #define ANX9804_SYS_CTRL3_F_HPD BIT(5) |
| 29 | |
| 30 | #define ANX9804_LINK_BW_SET_REG 0xa0 |
| 31 | #define ANX9804_LANE_COUNT_SET_REG 0xa1 |
| 32 | #define ANX9804_TRAINING_PTN_SET_REG 0xa2 |
| 33 | #define ANX9804_TRAINING_LANE0_SET_REG 0xa3 |
| 34 | #define ANX9804_TRAINING_LANE1_SET_REG 0xa4 |
| 35 | #define ANX9804_TRAINING_LANE2_SET_REG 0xa5 |
| 36 | #define ANX9804_TRAINING_LANE3_SET_REG 0xa6 |
| 37 | |
| 38 | #define ANX9804_LINK_TRAINING_CTRL_REG 0xa8 |
| 39 | #define ANX9804_LINK_TRAINING_CTRL_EN BIT(0) |
| 40 | |
| 41 | #define ANX9804_LINK_DEBUG_REG 0xb8 |
| 42 | #define ANX9804_PLL_CTRL_REG 0xc7 |
| 43 | #define ANX9804_ANALOG_POWER_DOWN_REG 0xc8 |
| 44 | |
| 45 | #define ANX9804_AUX_CH_STA 0xe0 |
| 46 | #define ANX9804_AUX_BUSY BIT(4) |
| 47 | #define ANX9804_AUX_STATUS_MASK 0x0f |
| 48 | |
| 49 | #define ANX9804_DP_AUX_RX_COMM 0xe3 |
| 50 | #define ANX9804_AUX_RX_COMM_I2C_DEFER BIT(3) |
| 51 | #define ANX9804_AUX_RX_COMM_AUX_DEFER BIT(1) |
| 52 | |
| 53 | #define ANX9804_DP_AUX_CH_CTL_1 0xe5 |
| 54 | #define ANX9804_AUX_LENGTH(x) (((x - 1) & 0x0f) << 4) |
| 55 | #define ANX9804_AUX_TX_COMM_MASK 0x0f |
| 56 | #define ANX9804_AUX_TX_COMM_DP_TRANSACTION BIT(3) |
| 57 | #define ANX9804_AUX_TX_COMM_MOT BIT(2) |
| 58 | #define ANX9804_AUX_TX_COMM_READ BIT(0) |
| 59 | |
| 60 | #define ANX9804_DP_AUX_ADDR_7_0 0xe6 |
| 61 | #define ANX9804_DP_AUX_ADDR_15_8 0xe7 |
| 62 | #define ANX9804_DP_AUX_ADDR_19_16 0xe8 |
| 63 | |
| 64 | #define ANX9804_DP_AUX_CH_CTL_2 0xe9 |
| 65 | #define ANX9804_ADDR_ONLY BIT(1) |
| 66 | #define ANX9804_AUX_EN BIT(0) |
| 67 | |
| 68 | #define ANX9804_BUF_DATA_0 0xf0 |
| 69 | |
| 70 | /* Registers at i2c address 0x39 */ |
| 71 | |
| 72 | #define ANX9804_DEV_IDH_REG 0x03 |
| 73 | |
| 74 | #define ANX9804_POWERD_CTRL_REG 0x05 |
| 75 | #define ANX9804_POWERD_AUDIO BIT(4) |
| 76 | |
| 77 | #define ANX9804_RST_CTRL_REG 0x06 |
| 78 | |
| 79 | #define ANX9804_RST_CTRL2_REG 0x07 |
| 80 | #define ANX9804_RST_CTRL2_AUX BIT(2) |
| 81 | #define ANX9804_RST_CTRL2_AC_MODE BIT(6) |
| 82 | |
| 83 | #define ANX9804_VID_CTRL1_REG 0x08 |
| 84 | #define ANX9804_VID_CTRL1_VID_EN BIT(7) |
| 85 | #define ANX9804_VID_CTRL1_EDGE BIT(0) |
| 86 | |
| 87 | #define ANX9804_VID_CTRL2_REG 0x09 |
| 88 | #define ANX9804_ANALOG_DEBUG_REG1 0xdc |
| 89 | #define ANX9804_ANALOG_DEBUG_REG3 0xde |
| 90 | #define ANX9804_PLL_FILTER_CTRL1 0xdf |
| 91 | #define ANX9804_PLL_FILTER_CTRL3 0xe1 |
| 92 | #define ANX9804_PLL_FILTER_CTRL 0xe2 |
| 93 | #define ANX9804_PLL_CTRL3 0xe6 |
| 94 | |
| 95 | #define ANX9804_DP_INT_STA 0xf7 |
| 96 | #define ANX9804_RPLY_RECEIV BIT(1) |
| 97 | #define ANX9804_AUX_ERR BIT(0) |