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git01.mediatek.com / filogic / uboot / 10e4779db8ae6c2784392fa7a1f690645918662d / . / board / sbc8548 / law.c
blob: 97271ea6f66be355ba467320820a1987505f7ad6 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0+
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]2/*
3 * Copyright 2008 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2000
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]7 */
8
9#include <common.h>
10#include <asm/fsl_law.h>
11#include <asm/mmu.h>
12
13/*
14 * LAW(Local Access Window) configuration:
15 *
16 * 0x0000_0000 0x0fff_ffff DDR 256M
17 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
Paul Gortmaker3bff6422009-09-20 20:36:05 -0400[diff] [blame]18 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]19 * 0xe000_0000 0xe000_ffff CCSR 1M
Paul Gortmaker3bff6422009-09-20 20:36:05 -0400[diff] [blame]20 * 0xe200_0000 0xe27f_ffff PCI1 IO 8M
21 * 0xe280_0000 0xe2ff_ffff PCIe IO 8M
Paul Gortmakera6d378a2011-12-30 23:53:07 -0500[diff] [blame]22 * 0xec00_0000 0xefff_ffff FLASH (2nd bank) 64M
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]23 * 0xf000_0000 0xf7ff_ffff SDRAM 128M
24 * 0xf8b0_0000 0xf80f_ffff EEPROM 1M
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]25 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
26 *
Paul Gortmaker626fa262011-12-30 23:53:08 -0500[diff] [blame]27 * If swapped CS0/CS6 via JP12+SW2.8:
28 * 0xef80_0000 0xefff_ffff FLASH (2nd bank) 8M
29 * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
30 *
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]31 * Notes:
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]32 * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]33 * If flash is 8M at default position (last 8M), no LAW needed.
34 */
35
36struct law_entry law_table[] = {
Paul Gortmaker626fa262011-12-30 23:53:08 -0500[diff] [blame]37#ifdef CONFIG_SYS_ALT_BOOT
38 SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
39#else
Paul Gortmakera6d378a2011-12-30 23:53:07 -0500[diff] [blame]40 SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
Paul Gortmaker626fa262011-12-30 23:53:08 -0500[diff] [blame]41#endif
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]42#ifndef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]43 SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]44#endif
Paul Gortmaker17f91842011-12-30 23:53:10 -0500[diff] [blame]45#ifdef CONFIG_SYS_LBC_SDRAM_BASE
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]46 /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]47 SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
Paul Gortmaker17f91842011-12-30 23:53:10 -0500[diff] [blame]48#else
49 /* LBC window - maps 128M 0xf8000000 -> 0xffffffff */
50 SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
51#endif
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]52};
53
54int num_law_entries = ARRAY_SIZE(law_table);