Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2015 Freescale Semiconductor, Inc. |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <fsl_ddr_sdram.h> |
| 8 | #include <fsl_ddr_dimm_params.h> |
York Sun | cbe8e1c | 2016-04-04 11:41:26 -0700 | [diff] [blame] | 9 | #include <asm/arch/soc.h> |
Simon Glass | 243182c | 2017-05-17 08:23:06 -0600 | [diff] [blame] | 10 | #include <asm/arch/clock.h> |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 11 | #include "ddr.h" |
| 12 | |
| 13 | DECLARE_GLOBAL_DATA_PTR; |
| 14 | |
| 15 | void fsl_ddr_board_options(memctl_options_t *popts, |
| 16 | dimm_params_t *pdimm, |
| 17 | unsigned int ctrl_num) |
| 18 | { |
Prabhakar Kushwaha | 122bcfd | 2015-11-09 16:42:07 +0530 | [diff] [blame] | 19 | #ifdef CONFIG_SYS_FSL_HAS_DP_DDR |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 20 | u8 dq_mapping_0, dq_mapping_2, dq_mapping_3; |
Prabhakar Kushwaha | 122bcfd | 2015-11-09 16:42:07 +0530 | [diff] [blame] | 21 | #endif |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 22 | const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; |
| 23 | ulong ddr_freq; |
| 24 | int slot; |
| 25 | |
| 26 | if (ctrl_num > 2) { |
| 27 | printf("Not supported controller number %d\n", ctrl_num); |
| 28 | return; |
| 29 | } |
| 30 | |
| 31 | for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) { |
| 32 | if (pdimm[slot].n_ranks) |
| 33 | break; |
| 34 | } |
| 35 | |
| 36 | if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR) |
| 37 | return; |
| 38 | |
| 39 | /* |
| 40 | * we use identical timing for all slots. If needed, change the code |
| 41 | * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; |
| 42 | */ |
| 43 | if (popts->registered_dimm_en) |
| 44 | pbsp = rdimms[ctrl_num]; |
| 45 | else |
| 46 | pbsp = udimms[ctrl_num]; |
| 47 | |
| 48 | |
| 49 | /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr |
| 50 | * freqency and n_banks specified in board_specific_parameters table. |
| 51 | */ |
| 52 | ddr_freq = get_ddr_freq(ctrl_num) / 1000000; |
| 53 | while (pbsp->datarate_mhz_high) { |
| 54 | if (pbsp->n_ranks == pdimm[slot].n_ranks && |
| 55 | (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) { |
| 56 | if (ddr_freq <= pbsp->datarate_mhz_high) { |
| 57 | popts->clk_adjust = pbsp->clk_adjust; |
| 58 | popts->wrlvl_start = pbsp->wrlvl_start; |
| 59 | popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
| 60 | popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
| 61 | goto found; |
| 62 | } |
| 63 | pbsp_highest = pbsp; |
| 64 | } |
| 65 | pbsp++; |
| 66 | } |
| 67 | |
| 68 | if (pbsp_highest) { |
| 69 | printf("Error: board specific timing not found for data rate %lu MT/s\n" |
| 70 | "Trying to use the highest speed (%u) parameters\n", |
| 71 | ddr_freq, pbsp_highest->datarate_mhz_high); |
| 72 | popts->clk_adjust = pbsp_highest->clk_adjust; |
| 73 | popts->wrlvl_start = pbsp_highest->wrlvl_start; |
| 74 | popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
| 75 | popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
| 76 | } else { |
| 77 | panic("DIMM is not supported by this board"); |
| 78 | } |
| 79 | found: |
| 80 | debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" |
| 81 | "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", |
| 82 | pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, |
| 83 | pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, |
| 84 | pbsp->wrlvl_ctl_3); |
Prabhakar Kushwaha | 122bcfd | 2015-11-09 16:42:07 +0530 | [diff] [blame] | 85 | #ifdef CONFIG_SYS_FSL_HAS_DP_DDR |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 86 | if (ctrl_num == CONFIG_DP_DDR_CTRL) { |
| 87 | /* force DDR bus width to 32 bits */ |
| 88 | popts->data_bus_width = 1; |
| 89 | popts->otf_burst_chop_en = 0; |
| 90 | popts->burst_length = DDR_BL8; |
| 91 | popts->bstopre = 0; /* enable auto precharge */ |
| 92 | /* |
| 93 | * Layout optimization results byte mapping |
| 94 | * Byte 0 -> Byte ECC |
| 95 | * Byte 1 -> Byte 3 |
| 96 | * Byte 2 -> Byte 2 |
| 97 | * Byte 3 -> Byte 1 |
| 98 | * Byte ECC -> Byte 0 |
| 99 | */ |
| 100 | dq_mapping_0 = pdimm[slot].dq_mapping[0]; |
| 101 | dq_mapping_2 = pdimm[slot].dq_mapping[2]; |
| 102 | dq_mapping_3 = pdimm[slot].dq_mapping[3]; |
| 103 | pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8]; |
| 104 | pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9]; |
| 105 | pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6]; |
| 106 | pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7]; |
| 107 | pdimm[slot].dq_mapping[6] = dq_mapping_2; |
| 108 | pdimm[slot].dq_mapping[7] = dq_mapping_3; |
| 109 | pdimm[slot].dq_mapping[8] = dq_mapping_0; |
| 110 | pdimm[slot].dq_mapping[9] = 0; |
| 111 | pdimm[slot].dq_mapping[10] = 0; |
| 112 | pdimm[slot].dq_mapping[11] = 0; |
| 113 | pdimm[slot].dq_mapping[12] = 0; |
| 114 | pdimm[slot].dq_mapping[13] = 0; |
| 115 | pdimm[slot].dq_mapping[14] = 0; |
| 116 | pdimm[slot].dq_mapping[15] = 0; |
| 117 | pdimm[slot].dq_mapping[16] = 0; |
| 118 | pdimm[slot].dq_mapping[17] = 0; |
| 119 | } |
Prabhakar Kushwaha | 122bcfd | 2015-11-09 16:42:07 +0530 | [diff] [blame] | 120 | #endif |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 121 | /* To work at higher than 1333MT/s */ |
| 122 | popts->half_strength_driver_enable = 0; |
| 123 | /* |
| 124 | * Write leveling override |
| 125 | */ |
| 126 | popts->wrlvl_override = 1; |
| 127 | popts->wrlvl_sample = 0x0; /* 32 clocks */ |
| 128 | |
| 129 | /* |
| 130 | * Rtt and Rtt_WR override |
| 131 | */ |
| 132 | popts->rtt_override = 0; |
| 133 | |
| 134 | /* Enable ZQ calibration */ |
| 135 | popts->zq_en = 1; |
| 136 | |
| 137 | if (ddr_freq < 2350) { |
York Sun | ce82a27 | 2015-11-04 10:03:22 -0800 | [diff] [blame] | 138 | if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) { |
| 139 | /* four chip-selects */ |
| 140 | popts->ddr_cdr1 = DDR_CDR1_DHC_EN | |
| 141 | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); |
| 142 | popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm); |
| 143 | popts->twot_en = 1; /* enable 2T timing */ |
| 144 | } else { |
| 145 | popts->ddr_cdr1 = DDR_CDR1_DHC_EN | |
| 146 | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); |
| 147 | popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | |
| 148 | DDR_CDR2_VREF_RANGE_2; |
| 149 | } |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 150 | } else { |
| 151 | popts->ddr_cdr1 = DDR_CDR1_DHC_EN | |
| 152 | DDR_CDR1_ODT(DDR_CDR_ODT_100ohm); |
| 153 | popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) | |
| 154 | DDR_CDR2_VREF_RANGE_2; |
| 155 | } |
| 156 | } |
| 157 | |
Simon Glass | 0e0ac20 | 2017-04-06 12:47:04 -0600 | [diff] [blame] | 158 | int fsl_initdram(void) |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 159 | { |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 160 | #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 161 | gd->ram_size = fsl_ddr_sdram_size(); |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 162 | #else |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 163 | puts("Initializing DDR....using SPD\n"); |
| 164 | |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 165 | gd->ram_size = fsl_ddr_sdram(); |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 166 | #endif |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 167 | |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 168 | return 0; |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 169 | } |