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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -05002/*
3 *
4 * (C) Copyright 2000-2003
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
Alison Wang8d8dac92012-03-26 21:49:08 +00007 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -05008 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -05009 */
10
11#include <common.h>
12#include <watchdog.h>
13#include <command.h>
Ben Warren2f2b6b62008-08-31 22:22:04 -070014#include <netdev.h>
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -050015
16#include <asm/immap.h>
Alison Wang8d8dac92012-03-26 21:49:08 +000017#include <asm/io.h>
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -050018
19DECLARE_GLOBAL_DATA_PTR;
20
Mike Frysinger6d1f6982010-10-20 03:41:17 -040021int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -050022{
Alison Wang8d8dac92012-03-26 21:49:08 +000023 rcm_t *rcm = (rcm_t *) (MMAP_RCM);
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -050024 udelay(1000);
Alison Wangfdc2fb12012-10-18 19:25:51 +000025 out_8(&rcm->rcr, RCM_RCR_FRCRSTOUT);
26 udelay(10000);
Alison Wang8d8dac92012-03-26 21:49:08 +000027 setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -050028
29 /* we don't return! */
30 return 0;
31};
32
Angelo Dureghello3146b4d2017-08-20 00:01:55 +020033#if defined(CONFIG_DISPLAY_CPUINFO)
34int print_cpuinfo(void)
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -050035{
Alison Wang8d8dac92012-03-26 21:49:08 +000036 ccm_t *ccm = (ccm_t *) MMAP_CCM;
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -050037 u16 msk;
38 u16 id = 0;
39 u8 ver;
40
41 puts("CPU: ");
Alison Wang8d8dac92012-03-26 21:49:08 +000042 msk = (in_be16(&ccm->cir) >> 6);
43 ver = (in_be16(&ccm->cir) & 0x003f);
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -050044 switch (msk) {
45 case 0x48:
46 id = 54455;
47 break;
48 case 0x49:
49 id = 54454;
50 break;
51 case 0x4a:
52 id = 54453;
53 break;
54 case 0x4b:
55 id = 54452;
56 break;
57 case 0x4d:
58 id = 54451;
59 break;
60 case 0x4f:
61 id = 54450;
62 break;
Alison Wangfdc2fb12012-10-18 19:25:51 +000063 case 0x9F:
64 id = 54410;
65 break;
66 case 0xA0:
67 id = 54415;
68 break;
69 case 0xA1:
70 id = 54416;
71 break;
72 case 0xA2:
73 id = 54417;
74 break;
75 case 0xA3:
76 id = 54418;
77 break;
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -050078 }
79
80 if (id) {
Wolfgang Denk20591042008-10-19 02:35:49 +020081 char buf1[32], buf2[32], buf3[32];
82
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -050083 printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
84 ver);
Wolfgang Denk20591042008-10-19 02:35:49 +020085 printf(" CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
86 strmhz(buf1, gd->cpu_clk),
87 strmhz(buf2, gd->bus_clk),
Simon Glass568a7b62012-12-13 20:49:07 +000088 strmhz(buf3, gd->arch.flb_clk));
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -050089#ifdef CONFIG_PCI
Wolfgang Denk20591042008-10-19 02:35:49 +020090 printf(" PCI CLK %s MHz INP CLK %s MHz VCO CLK %s MHz\n",
91 strmhz(buf1, gd->pci_clk),
Simon Glass568a7b62012-12-13 20:49:07 +000092 strmhz(buf2, gd->arch.inp_clk),
93 strmhz(buf3, gd->arch.vco_clk));
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -050094#else
Wolfgang Denk20591042008-10-19 02:35:49 +020095 printf(" INP CLK %s MHz VCO CLK %s MHz\n",
Simon Glass568a7b62012-12-13 20:49:07 +000096 strmhz(buf1, gd->arch.inp_clk),
97 strmhz(buf2, gd->arch.vco_clk));
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -050098#endif
99 }
100
101 return 0;
102}
Angelo Dureghello3146b4d2017-08-20 00:01:55 +0200103#endif /* CONFIG_DISPLAY_CPUINFO */
Ben Warren90c96db2008-08-26 22:16:25 -0700104
105#if defined(CONFIG_MCFFEC)
106/* Default initializations for MCFFEC controllers. To override,
107 * create a board-specific function called:
108 * int board_eth_init(bd_t *bis)
109 */
110
Ben Warren90c96db2008-08-26 22:16:25 -0700111int cpu_eth_init(bd_t *bis)
112{
113 return mcffec_initialize(bis);
114}
115#endif