Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2004 Texas Insturments |
| 4 | * |
| 5 | * (C) Copyright 2002 |
| 6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 7 | * Marius Groeger <mgroeger@sysgo.de> |
| 8 | * |
| 9 | * (C) Copyright 2002 |
Detlev Zundel | f1b3f2b | 2009-05-13 10:54:10 +0200 | [diff] [blame] | 10 | * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * CPU specific code |
| 15 | */ |
| 16 | |
| 17 | #include <common.h> |
| 18 | #include <command.h> |
Jean-Christophe PLAGNIOL-VILLARD | 9053b5a | 2009-04-05 13:02:43 +0200 | [diff] [blame] | 19 | #include <asm/system.h> |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 20 | |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 21 | static void cache_flush(void); |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 22 | |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 23 | int cleanup_before_linux (void) |
| 24 | { |
| 25 | /* |
| 26 | * this function is called just before we call linux |
| 27 | * it prepares the processor for linux |
| 28 | * |
| 29 | * we turn off caches etc ... |
| 30 | */ |
| 31 | |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 32 | disable_interrupts (); |
| 33 | |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 34 | /* turn off I/D-cache */ |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 35 | icache_disable(); |
| 36 | dcache_disable(); |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 37 | /* flush I/D-cache */ |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 38 | cache_flush(); |
| 39 | |
| 40 | return 0; |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 41 | } |
| 42 | |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 43 | static void cache_flush(void) |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 44 | { |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 45 | unsigned long i = 0; |
Stefano Babic | 9e39793 | 2012-04-09 13:33:04 +0200 | [diff] [blame] | 46 | /* clean entire data cache */ |
| 47 | asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i)); |
| 48 | /* invalidate both caches and flush btb */ |
| 49 | asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i)); |
| 50 | /* mem barrier to sync things */ |
| 51 | asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i)); |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 52 | } |
Anatolij Gustschin | 02966ca | 2012-04-02 06:18:00 +0000 | [diff] [blame] | 53 | |
| 54 | #ifndef CONFIG_SYS_DCACHE_OFF |
Anatolij Gustschin | 02966ca | 2012-04-02 06:18:00 +0000 | [diff] [blame] | 55 | void invalidate_dcache_all(void) |
| 56 | { |
Stefano Babic | 9e39793 | 2012-04-09 13:33:04 +0200 | [diff] [blame] | 57 | asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); |
Anatolij Gustschin | 02966ca | 2012-04-02 06:18:00 +0000 | [diff] [blame] | 58 | } |
| 59 | |
| 60 | void flush_dcache_all(void) |
| 61 | { |
Stefano Babic | 9e39793 | 2012-04-09 13:33:04 +0200 | [diff] [blame] | 62 | asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0)); |
| 63 | asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); |
Anatolij Gustschin | 02966ca | 2012-04-02 06:18:00 +0000 | [diff] [blame] | 64 | } |
| 65 | |
Anatolij Gustschin | 02966ca | 2012-04-02 06:18:00 +0000 | [diff] [blame] | 66 | void invalidate_dcache_range(unsigned long start, unsigned long stop) |
| 67 | { |
Benoît Thébaudeau | 1053bd2 | 2012-07-19 01:35:32 +0000 | [diff] [blame] | 68 | if (!check_cache_range(start, stop)) |
Anatolij Gustschin | 02966ca | 2012-04-02 06:18:00 +0000 | [diff] [blame] | 69 | return; |
| 70 | |
| 71 | while (start < stop) { |
Stefano Babic | 9e39793 | 2012-04-09 13:33:04 +0200 | [diff] [blame] | 72 | asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)); |
Anatolij Gustschin | 02966ca | 2012-04-02 06:18:00 +0000 | [diff] [blame] | 73 | start += CONFIG_SYS_CACHELINE_SIZE; |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | void flush_dcache_range(unsigned long start, unsigned long stop) |
| 78 | { |
Benoît Thébaudeau | 1053bd2 | 2012-07-19 01:35:32 +0000 | [diff] [blame] | 79 | if (!check_cache_range(start, stop)) |
Anatolij Gustschin | 02966ca | 2012-04-02 06:18:00 +0000 | [diff] [blame] | 80 | return; |
| 81 | |
| 82 | while (start < stop) { |
Stefano Babic | 9e39793 | 2012-04-09 13:33:04 +0200 | [diff] [blame] | 83 | asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start)); |
Anatolij Gustschin | 02966ca | 2012-04-02 06:18:00 +0000 | [diff] [blame] | 84 | start += CONFIG_SYS_CACHELINE_SIZE; |
| 85 | } |
| 86 | |
Stefano Babic | 9e39793 | 2012-04-09 13:33:04 +0200 | [diff] [blame] | 87 | asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); |
Anatolij Gustschin | 02966ca | 2012-04-02 06:18:00 +0000 | [diff] [blame] | 88 | } |
| 89 | |
Anatolij Gustschin | 02966ca | 2012-04-02 06:18:00 +0000 | [diff] [blame] | 90 | #else /* #ifndef CONFIG_SYS_DCACHE_OFF */ |
| 91 | void invalidate_dcache_all(void) |
| 92 | { |
| 93 | } |
| 94 | |
| 95 | void flush_dcache_all(void) |
| 96 | { |
| 97 | } |
Anatolij Gustschin | 02966ca | 2012-04-02 06:18:00 +0000 | [diff] [blame] | 98 | #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ |
Benoît Thébaudeau | dbbd845 | 2012-10-04 10:04:02 +0000 | [diff] [blame] | 99 | |
| 100 | #if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF) |
| 101 | void enable_caches(void) |
| 102 | { |
| 103 | #ifndef CONFIG_SYS_ICACHE_OFF |
| 104 | icache_enable(); |
| 105 | #endif |
| 106 | #ifndef CONFIG_SYS_DCACHE_OFF |
| 107 | dcache_enable(); |
| 108 | #endif |
| 109 | } |
| 110 | #endif |