Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 10dda9ec7cfa0162558c8c5b3de64efe32ea7dac / . / configs / P1020RDB-PD_SPIFLASH_defconfig
blob: 432610983106e7213dd0357bb8ade94b57452cb8 [file] [log] [blame]
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]1CONFIG_PPC=y
Pali Rohár18209f72022-06-16 14:19:44 +0200[diff] [blame]2CONFIG_SYS_TEXT_BASE=0x11000000
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]3CONFIG_SYS_MALLOC_LEN=0x100000
Simon Glassf2a89462016-09-12 23:18:41 -0600[diff] [blame]4CONFIG_SPL_LIBCOMMON_SUPPORT=y
Simon Glassb16c92c2016-09-12 23:18:43 -0600[diff] [blame]5CONFIG_SPL_LIBGENERIC_SUPPORT=y
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]6CONFIG_ENV_SIZE=0x2000
7CONFIG_ENV_OFFSET=0x100000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]8CONFIG_ENV_SECT_SIZE=0x10000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]9CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
Pali Rohár18209f72022-06-16 14:19:44 +0200[diff] [blame]10CONFIG_SPL_TEXT_BASE=0xf8f80000
Simon Glassf4d60392021-08-08 12:20:12 -0600[diff] [blame]11CONFIG_SPL_SERIAL=y
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]12CONFIG_SPL=y
Simon Glass219d6122016-09-12 23:18:57 -0600[diff] [blame]13CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassa5820472021-08-08 12:20:14 -0600[diff] [blame]14CONFIG_SPL_SPI=y
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]15CONFIG_MPC85xx=y
Simon Glass9fdc0de2017-05-17 03:25:15 -0600[diff] [blame]16# CONFIG_CMD_ERRATA is not set
York Sun06732382016-11-17 13:53:33 -0800[diff] [blame]17CONFIG_TARGET_P1020RDB_PD=y
Tom Rinia7fa9762022-06-15 12:03:45 -0400[diff] [blame]18CONFIG_ENABLE_36BIT_PHYS=y
Tom Rini667dd4f2022-06-10 22:59:37 -0400[diff] [blame]19CONFIG_SYS_MPC85XX_NO_RESETVEC=y
20CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
Tom Rini7485ebf62022-06-20 08:07:45 -0400[diff] [blame]21CONFIG_PCIE1=y
22CONFIG_PCIE2=y
Tom Rini5ca768d2022-01-24 21:08:41 +0000[diff] [blame]23CONFIG_MP=y
Simon Glasse3ee2fb2016-02-22 22:55:43 -0700[diff] [blame]24CONFIG_FIT=y
25CONFIG_FIT_VERBOSE=y
26CONFIG_OF_BOARD_SETUP=y
27CONFIG_OF_STDOUT_VIA_ALIAS=y
Pali Rohár18209f72022-06-16 14:19:44 +0200[diff] [blame]28CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
Tom Rini886e6e32022-03-23 17:20:03 -0400[diff] [blame]29CONFIG_SPIFLASH=y
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]30CONFIG_BOOTDELAY=10
Tom Rini5ddf1722021-11-10 09:11:40 -0500[diff] [blame]31CONFIG_USE_BOOTCOMMAND=y
32CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
Simon Glass7a99a872017-01-23 13:31:20 -0700[diff] [blame]33CONFIG_BOARD_EARLY_INIT_F=y
Mario Six75b23ed2018-03-28 14:38:15 +0200[diff] [blame]34CONFIG_BOARD_EARLY_INIT_R=y
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]35# CONFIG_MISC_INIT_R is not set
Tom Rini623d67e2018-02-06 12:15:38 -0500[diff] [blame]36# CONFIG_SPL_FRAMEWORK is not set
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]37CONFIG_SPL_MAX_SIZE=0x20000
Tom Rinie5678e42019-06-01 14:20:25 -0400[diff] [blame]38CONFIG_SPL_SPI_BOOT=y
Tom Rini17845c52022-05-21 11:26:27 -0400[diff] [blame]39CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
Tom Rini6b15c162022-05-13 12:26:35 -0400[diff] [blame]40CONFIG_SPL_FLUSH_IMAGE=y
Tom Rinid75a7792022-05-27 16:19:05 -0400[diff] [blame]41CONFIG_SPL_GD_ADDR=0xf8f9c000
Tom Rini6de36a72022-05-26 16:59:30 -0400[diff] [blame]42CONFIG_SPL_RELOC_STACK=0xf8f9d000
43CONFIG_SPL_RELOC_MALLOC=y
44CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000
45CONFIG_SPL_RELOC_MALLOC_SIZE=0x1b000
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]46CONFIG_SPL_ENV_SUPPORT=y
Simon Glassbccfc2e2021-07-10 21:14:36 -0600[diff] [blame]47CONFIG_SPL_I2C=y
Simon Glass64571062021-08-08 12:20:16 -0600[diff] [blame]48CONFIG_SPL_MPC8XXX_INIT_DDR=y
Tom Rini06d06f72022-05-27 17:13:52 -0400[diff] [blame]49CONFIG_SPL_TARGET="u-boot-with-spl.bin"
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]50CONFIG_HUSH_PARSER=y
Adam Ford58dbf862018-02-06 07:58:59 -0600[diff] [blame]51# CONFIG_AUTO_COMPLETE is not set
Tom Rinicbfa1392022-05-11 17:38:09 -0400[diff] [blame]52CONFIG_SYS_PBSIZE=276
Tuomas Tynkkynen28d56bd2017-10-08 21:48:01 +0300[diff] [blame]53CONFIG_CMD_IMLS=y
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]54CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
55CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]56CONFIG_CMD_I2C=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]57CONFIG_CMD_MMC=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]58CONFIG_CMD_USB=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]59CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]60CONFIG_CMD_PING=y
Simon Glass027608e2017-05-17 03:25:25 -0600[diff] [blame]61# CONFIG_CMD_HASH is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]62CONFIG_CMD_EXT2=y
63CONFIG_CMD_FAT=y
Tom Rinic20bb732017-07-22 18:36:16 -0400[diff] [blame]64CONFIG_CMD_MTDPARTS=y
Tom Rini5ad8e112017-10-22 17:55:07 -0400[diff] [blame]65CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
66CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
Hou Zhiqiang224999f2019-08-20 09:35:28 +0000[diff] [blame]67CONFIG_OF_CONTROL=y
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]68CONFIG_ENV_OVERWRITE=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]69CONFIG_ENV_IS_IN_SPI_FLASH=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]70CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rini5fb860c2022-02-25 11:19:48 -0500[diff] [blame]71CONFIG_USE_BOOTFILE=y
72CONFIG_BOOTFILE="uImage"
Tom Rinife586752022-03-11 09:12:07 -0500[diff] [blame]73CONFIG_USE_ETHPRIME=y
74CONFIG_ETHPRIME="eTSEC1"
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]75CONFIG_DM=y
Tom Rini3f004772022-06-10 22:59:28 -0400[diff] [blame]76CONFIG_LBA48=y
Tom Rinif7246c22021-08-21 13:50:17 -0400[diff] [blame]77CONFIG_DDR_CLK_FREQ=66666666
Tom Riniafba4112022-06-15 12:03:54 -0400[diff] [blame]78CONFIG_SYS_SPD_BUS_NUM=1
Tom Rini56184602022-02-25 11:19:53 -0500[diff] [blame]79CONFIG_CHIP_SELECTS_PER_CTRL=2
Tom Rini8e99f7d2022-06-15 12:03:55 -0400[diff] [blame]80CONFIG_SYS_DDR_RAW_TIMING=y
Tom Rinif7eed202021-11-13 18:10:40 -0500[diff] [blame]81CONFIG_SYS_BR0_PRELIM_BOOL=y
82CONFIG_SYS_BR0_PRELIM=0xEC001001
83CONFIG_SYS_OR0_PRELIM=0xFC000FF7
84CONFIG_SYS_BR2_PRELIM_BOOL=y
85CONFIG_SYS_BR2_PRELIM=0xFFB00801
86CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
87CONFIG_SYS_BR3_PRELIM_BOOL=y
88CONFIG_SYS_BR3_PRELIM=0xFFA00801
89CONFIG_SYS_OR3_PRELIM=0xFFF009F7
Tom Rinif8f6b322022-05-21 14:44:28 -0400[diff] [blame]90CONFIG_SPL_COMMON_INIT_DDR=y
Tom Rini3eea5772020-05-08 09:08:39 -0400[diff] [blame]91CONFIG_DM_I2C=y
Tom Rini52b2e262021-08-18 23:12:24 -0400[diff] [blame]92CONFIG_SPL_SYS_I2C_LEGACY=y
Tom Rinib1b13072021-08-18 23:12:37 -0400[diff] [blame]93CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
Tom Rinibe94c762021-08-18 23:12:35 -0400[diff] [blame]94CONFIG_SYS_I2C_FSL=y
95CONFIG_SYS_FSL_I2C_OFFSET=0x3000
96CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
97CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]98CONFIG_SYS_I2C_EEPROM_ADDR=0x52
Mario Six41d7d972018-03-28 14:38:19 +0200[diff] [blame]99CONFIG_FSL_ESDHC=y
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame]100CONFIG_MTD=y
Adam Ford76da1b22018-10-14 15:10:50 -0500[diff] [blame]101CONFIG_MTD_NOR_FLASH=y
102CONFIG_FLASH_CFI_DRIVER=y
103CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
Tom Rini302bd672022-07-23 13:04:55 -0400[diff] [blame]104CONFIG_SYS_FLASH_EMPTY_INFO=y
Adam Ford76da1b22018-10-14 15:10:50 -0500[diff] [blame]105CONFIG_FLASH_CFI_MTD=y
106CONFIG_SYS_FLASH_CFI=y
Tom Rini2e35d822022-07-23 13:05:05 -0400[diff] [blame]107CONFIG_SYS_FLASH_QUIET_TEST=y
Tom Rini526e3c82020-10-05 13:11:41 -0400[diff] [blame]108CONFIG_DM_SPI_FLASH=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]109CONFIG_SF_DEFAULT_SPEED=10000000
Bin Meng27f5b192015-11-25 05:34:54 -0800[diff] [blame]110CONFIG_SPI_FLASH_SPANSION=y
Tom Rini5d154192020-04-24 15:35:53 -0400[diff] [blame]111CONFIG_PHY_ATHEROS=y
112CONFIG_PHY_BROADCOM=y
113CONFIG_PHY_DAVICOM=y
114CONFIG_PHY_LXT=y
Mario Sixf504d1a2018-04-27 14:52:21 +0200[diff] [blame]115CONFIG_PHY_MARVELL=y
Tom Rini5d154192020-04-24 15:35:53 -0400[diff] [blame]116CONFIG_PHY_NATSEMI=y
117CONFIG_PHY_REALTEK=y
118CONFIG_PHY_SMSC=y
119CONFIG_PHY_VITESSE=y
Tom Rini526e3c82020-10-05 13:11:41 -0400[diff] [blame]120CONFIG_PHY_FIXED=y
Tom Rini526e3c82020-10-05 13:11:41 -0400[diff] [blame]121CONFIG_DM_MDIO=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]122CONFIG_PHY_GIGE=y
Simon Glass9008a5b2015-08-19 09:33:43 -0600[diff] [blame]123CONFIG_E1000=y
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]124CONFIG_MII=y
125CONFIG_TSEC_ENET=y
Hou Zhiqiang38853312019-08-27 11:04:11 +0000[diff] [blame]126CONFIG_PCIE_FSL=y
Tom Rini3eea5772020-05-08 09:08:39 -0400[diff] [blame]127CONFIG_DM_RTC=y
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]128CONFIG_SYS_NS16550=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]129CONFIG_SPI=y
Tom Rini526e3c82020-10-05 13:11:41 -0400[diff] [blame]130CONFIG_DM_SPI=y
Bin Meng72a049d2015-11-25 05:34:53 -0800[diff] [blame]131CONFIG_FSL_ESPI=y
Tom Rini6e9cb112016-09-08 16:31:26 -0400[diff] [blame]132CONFIG_USB=y
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]133CONFIG_USB_EHCI_FSL=y
Tom Rini526e3c82020-10-05 13:11:41 -0400[diff] [blame]134CONFIG_USB_STORAGE=y