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git01.mediatek.com / filogic / uboot / e799f9215b3340cfb014d3a2de430fb335d26852 / . / configs / P1020RDB-PD_SPIFLASH_defconfig
blob: e936128d23b52d6425e214d8edd56eb3df9f3294 [file] [log] [blame]
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]1CONFIG_PPC=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]2CONFIG_SYS_TEXT_BASE=0x11001000
Simon Glassf2a89462016-09-12 23:18:41 -0600[diff] [blame]3CONFIG_SPL_LIBCOMMON_SUPPORT=y
Simon Glassb16c92c2016-09-12 23:18:43 -0600[diff] [blame]4CONFIG_SPL_LIBGENERIC_SUPPORT=y
Simon Glasse076d6f2016-09-12 23:18:56 -0600[diff] [blame]5CONFIG_SPL_SERIAL_SUPPORT=y
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]6CONFIG_ENV_SIZE=0x2000
7CONFIG_ENV_OFFSET=0x100000
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]8CONFIG_SPL=y
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]9CONFIG_ENV_SECT_SIZE=0x10000
Simon Glass219d6122016-09-12 23:18:57 -0600[diff] [blame]10CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassb24fdca2016-09-12 23:18:58 -0600[diff] [blame]11CONFIG_SPL_SPI_SUPPORT=y
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]12CONFIG_MPC85xx=y
Simon Glass9fdc0de2017-05-17 03:25:15 -0600[diff] [blame]13# CONFIG_CMD_ERRATA is not set
York Sun06732382016-11-17 13:53:33 -0800[diff] [blame]14CONFIG_TARGET_P1020RDB_PD=y
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]15CONFIG_SPL_TEXT_BASE=0xf8f81000
Simon Glasse3ee2fb2016-02-22 22:55:43 -0700[diff] [blame]16CONFIG_FIT=y
17CONFIG_FIT_VERBOSE=y
18CONFIG_OF_BOARD_SETUP=y
19CONFIG_OF_STDOUT_VIA_ALIAS=y
York Sun06732382016-11-17 13:53:33 -0800[diff] [blame]20CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]21CONFIG_BOOTDELAY=10
Adam Ford10541762018-07-29 13:13:29 -0500[diff] [blame]22# CONFIG_MISC_INIT_R is not set
Simon Glass7a99a872017-01-23 13:31:20 -0700[diff] [blame]23CONFIG_BOARD_EARLY_INIT_F=y
Mario Six75b23ed2018-03-28 14:38:15 +0200[diff] [blame]24CONFIG_BOARD_EARLY_INIT_R=y
Tom Rini623d67e2018-02-06 12:15:38 -0500[diff] [blame]25# CONFIG_SPL_FRAMEWORK is not set
Tom Rinie5678e42019-06-01 14:20:25 -0400[diff] [blame]26CONFIG_SPL_SPI_BOOT=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]27CONFIG_SPL_ENV_SUPPORT=y
28CONFIG_SPL_I2C_SUPPORT=y
Simon Glass7db65a82016-09-12 23:18:45 -0600[diff] [blame]29CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]30CONFIG_HUSH_PARSER=y
Adam Ford58dbf862018-02-06 07:58:59 -0600[diff] [blame]31# CONFIG_AUTO_COMPLETE is not set
Tuomas Tynkkynen28d56bd2017-10-08 21:48:01 +0300[diff] [blame]32CONFIG_CMD_IMLS=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]33CONFIG_CMD_I2C=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]34CONFIG_CMD_MMC=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]35CONFIG_CMD_SF=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]36CONFIG_CMD_USB=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]37CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]38CONFIG_CMD_PING=y
Chris Packham3e257df2017-04-29 15:20:28 +1200[diff] [blame]39CONFIG_CMD_DATE=y
Siva Durga Prasad Paladugu8e45f1a2018-06-19 12:24:23 +0200[diff] [blame]40CONFIG_MP=y
Simon Glass027608e2017-05-17 03:25:25 -0600[diff] [blame]41# CONFIG_CMD_HASH is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]42CONFIG_CMD_EXT2=y
43CONFIG_CMD_FAT=y
Tom Rinic20bb732017-07-22 18:36:16 -0400[diff] [blame]44CONFIG_CMD_MTDPARTS=y
Tom Rini5ad8e112017-10-22 17:55:07 -0400[diff] [blame]45CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
46CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
Hou Zhiqiang224999f2019-08-20 09:35:28 +0000[diff] [blame]47CONFIG_OF_CONTROL=y
48CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]49CONFIG_ENV_IS_IN_SPI_FLASH=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]50CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]51CONFIG_DM=y
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame^]52CONFIG_DM_MMC=y
Mario Six41d7d972018-03-28 14:38:19 +0200[diff] [blame]53CONFIG_FSL_ESDHC=y
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame^]54CONFIG_MTD=y
Adam Ford76da1b22018-10-14 15:10:50 -0500[diff] [blame]55CONFIG_MTD_NOR_FLASH=y
56CONFIG_FLASH_CFI_DRIVER=y
57CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
58CONFIG_FLASH_CFI_MTD=y
59CONFIG_SYS_FLASH_CFI=y
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]60CONFIG_SPI_FLASH=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]61CONFIG_SF_DEFAULT_MODE=0
62CONFIG_SF_DEFAULT_SPEED=10000000
Bin Meng27f5b192015-11-25 05:34:54 -0800[diff] [blame]63CONFIG_SPI_FLASH_SPANSION=y
Mario Sixf504d1a2018-04-27 14:52:21 +0200[diff] [blame]64CONFIG_PHY_MARVELL=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]65CONFIG_PHY_GIGE=y
Simon Glass9008a5b2015-08-19 09:33:43 -0600[diff] [blame]66CONFIG_E1000=y
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]67CONFIG_MII=y
68CONFIG_TSEC_ENET=y
Hou Zhiqiang38853312019-08-27 11:04:11 +0000[diff] [blame]69CONFIG_DM_PCI=y
70CONFIG_DM_PCI_COMPAT=y
71CONFIG_PCIE_FSL=y
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]72CONFIG_SYS_NS16550=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]73CONFIG_SPI=y
Bin Meng72a049d2015-11-25 05:34:53 -0800[diff] [blame]74CONFIG_FSL_ESPI=y
Tom Rini6e9cb112016-09-08 16:31:26 -0400[diff] [blame]75CONFIG_USB=y