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git01.mediatek.com / filogic / uboot / 0fea34e24d8a4e933653a041166f263258fdd0b4 / . / arch / riscv / dts / fu540-c000-u-boot.dtsi
blob: 360679a1781a9352528726a21c168c2a8082a7b7 [file] [log] [blame]
Pragnesh Patel2a449a32020-05-29 11:33:22 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * (C) Copyright 2019 SiFive, Inc
4 */
5
Sagar Shrikant Kadamb0357f42020-07-29 02:36:12 -0700[diff] [blame]6#include <dt-bindings/reset/sifive-fu540-prci.h>
7
Pragnesh Patel2a449a32020-05-29 11:33:22 +0530[diff] [blame]8/ {
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]9 cpus {
10 assigned-clocks = <&prci PRCI_CLK_COREPLL>;
11 assigned-clock-rates = <1000000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]12 bootph-pre-ram;
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]13 cpu0: cpu@0 {
14 clocks = <&prci PRCI_CLK_COREPLL>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]15 bootph-pre-ram;
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]16 status = "okay";
17 cpu0_intc: interrupt-controller {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-pre-ram;
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]19 };
20 };
21 cpu1: cpu@1 {
22 clocks = <&prci PRCI_CLK_COREPLL>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]23 bootph-pre-ram;
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]24 cpu1_intc: interrupt-controller {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-pre-ram;
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]26 };
27 };
28 cpu2: cpu@2 {
29 clocks = <&prci PRCI_CLK_COREPLL>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]31 cpu2_intc: interrupt-controller {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-pre-ram;
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]33 };
34 };
35 cpu3: cpu@3 {
36 clocks = <&prci PRCI_CLK_COREPLL>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]38 cpu3_intc: interrupt-controller {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-pre-ram;
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]40 };
41 };
42 cpu4: cpu@4 {
43 clocks = <&prci PRCI_CLK_COREPLL>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-pre-ram;
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]45 cpu4_intc: interrupt-controller {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]47 };
48 };
49 };
50
Pragnesh Patel2a449a32020-05-29 11:33:22 +0530[diff] [blame]51 soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]52 bootph-pre-ram;
Pragnesh Patel2a449a32020-05-29 11:33:22 +0530[diff] [blame]53 otp: otp@10070000 {
54 compatible = "sifive,fu540-c000-otp";
Bin Meng3961e142020-06-08 20:28:26 -0700[diff] [blame]55 reg = <0x0 0x10070000 0x0 0x1000>;
Pragnesh Patel2a449a32020-05-29 11:33:22 +0530[diff] [blame]56 fuse-count = <0x1000>;
57 };
Sean Anderson3d9991942020-09-28 10:52:29 -0400[diff] [blame]58 clint: clint@2000000 {
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]59 compatible = "riscv,clint0";
Sean Anderson3d9991942020-09-28 10:52:29 -0400[diff] [blame]60 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
61 &cpu1_intc 3 &cpu1_intc 7
62 &cpu2_intc 3 &cpu2_intc 7
63 &cpu3_intc 3 &cpu3_intc 7
64 &cpu4_intc 3 &cpu4_intc 7>;
Pragnesh Patel2dc59842020-10-20 11:03:02 +0530[diff] [blame]65 reg = <0x0 0x2000000 0x0 0x10000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-pre-ram;
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]67 };
Sagar Shrikant Kadamb0357f42020-07-29 02:36:12 -0700[diff] [blame]68 prci: clock-controller@10000000 {
69 #reset-cells = <1>;
70 resets = <&prci PRCI_RST_DDR_CTRL_N>,
71 <&prci PRCI_RST_DDR_AXI_N>,
72 <&prci PRCI_RST_DDR_AHB_N>,
73 <&prci PRCI_RST_DDR_PHY_N>,
74 <&prci PRCI_RST_GEMGXL_N>;
75 reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
76 "ddr_phy", "gemgxl_reset";
77 };
Pragnesh Patel45ffc912020-05-29 11:33:28 +0530[diff] [blame]78 dmc: dmc@100b0000 {
79 compatible = "sifive,fu540-c000-ddr";
80 reg = <0x0 0x100b0000 0x0 0x0800
81 0x0 0x100b2000 0x0 0x2000
Bin Meng3961e142020-06-08 20:28:26 -0700[diff] [blame]82 0x0 0x100b8000 0x0 0x1000>;
Pragnesh Patel45ffc912020-05-29 11:33:28 +0530[diff] [blame]83 clocks = <&prci PRCI_CLK_DDRPLL>;
84 clock-frequency = <933333324>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Pragnesh Patel45ffc912020-05-29 11:33:28 +0530[diff] [blame]86 };
Pragnesh Patel2a449a32020-05-29 11:33:22 +0530[diff] [blame]87 };
88};
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]89
90&prci {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-pre-ram;
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]92};
93
94&uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-pre-ram;
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]96};
97
98&qspi2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]99 bootph-pre-ram;
Pragnesh Patelb65f19f2020-05-29 11:33:25 +0530[diff] [blame]100};
Pragnesh Patelbb337f92020-05-29 11:33:32 +0530[diff] [blame]101
102&eth0 {
103 assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
104 assigned-clock-rates = <125000000>;
105};
Pragnesh Patel8a521282020-05-29 12:14:51 +0530[diff] [blame]106
107&l2cache {
108 status = "okay";
109};