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Michal Simek71d84b42018-03-27 13:43:05 +02001// SPDX-License-Identifier: GPL-2.0+
Jagannadha Sutradharudu Tekifc0d22b2014-01-09 01:48:29 +05302/*
3 * Xilinx ZC770 XM012 board DTS
4 *
Michal Simek71d84b42018-03-27 13:43:05 +02005 * Copyright (C) 2013-2018 Xilinx, Inc.
Jagannadha Sutradharudu Tekifc0d22b2014-01-09 01:48:29 +05306 */
7/dts-v1/;
8#include "zynq-7000.dtsi"
9
10/ {
Jagannadha Sutradharudu Tekifc0d22b2014-01-09 01:48:29 +053011 compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
Michal Simek1b27e662015-07-22 11:36:32 +020012 model = "Xilinx Zynq";
Masahiro Yamadad6367a22014-05-15 20:37:54 +090013
Masahiro Yamada87f645e2014-05-15 20:37:55 +090014 aliases {
Michal Simek1b27e662015-07-22 11:36:32 +020015 i2c0 = &i2c0;
16 i2c1 = &i2c1;
Masahiro Yamada87f645e2014-05-15 20:37:55 +090017 serial0 = &uart1;
Michal Simek1b27e662015-07-22 11:36:32 +020018 spi0 = &spi1;
Masahiro Yamada87f645e2014-05-15 20:37:55 +090019 };
20
Michal Simek1b27e662015-07-22 11:36:32 +020021 chosen {
Michal Simek8073b862016-04-07 11:15:00 +020022 bootargs = "";
Michal Simekc9af95a2016-01-12 13:56:44 +010023 stdout-path = "serial0:115200n8";
Michal Simek1b27e662015-07-22 11:36:32 +020024 };
25
Michal Simekb3585f42016-11-11 13:11:37 +010026 memory@0 {
Masahiro Yamadad6367a22014-05-15 20:37:54 +090027 device_type = "memory";
Michal Simek1b27e662015-07-22 11:36:32 +020028 reg = <0x0 0x40000000>;
Masahiro Yamadad6367a22014-05-15 20:37:54 +090029 };
Jagannadha Sutradharudu Tekifc0d22b2014-01-09 01:48:29 +053030};
Michal Simek1b27e662015-07-22 11:36:32 +020031
Michal Simek1b27e662015-07-22 11:36:32 +020032&can1 {
33 status = "okay";
34};
35
36&i2c0 {
37 status = "okay";
38 clock-frequency = <400000>;
39
Michal Simekf69db102018-03-27 13:48:51 +020040 eeprom0: eeprom@52 {
41 compatible = "atmel,24c02";
Michal Simek1b27e662015-07-22 11:36:32 +020042 reg = <0x52>;
43 };
44};
45
46&i2c1 {
47 status = "okay";
48 clock-frequency = <400000>;
49
Michal Simekf69db102018-03-27 13:48:51 +020050 eeprom1: eeprom@52 {
51 compatible = "atmel,24c02";
Michal Simek1b27e662015-07-22 11:36:32 +020052 reg = <0x52>;
53 };
54};
55
Michal Simek49f44b92016-01-14 13:09:16 +010056&spi1 {
57 status = "okay";
58 num-cs = <4>;
59 is-decoded-cs = <0>;
60};
61
Michal Simek1b27e662015-07-22 11:36:32 +020062&uart1 {
Simon Glass8c7323a2015-10-17 19:41:24 -060063 u-boot,dm-pre-reloc;
Michal Simek1b27e662015-07-22 11:36:32 +020064 status = "okay";
65};