blob: b8d5dd156f9f75a61ea7d921ff74b694dcc1d59b [file] [log] [blame]
Stelian Pop0bf5cad2008-05-08 18:52:25 +02001/*
2 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Stelian Pop0bf5cad2008-05-08 18:52:25 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * Configuation settings for the AT91SAM9RLEK board.
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Stelian Pop0bf5cad2008-05-08 18:52:25 +02009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Xu, Hong0c0fb212011-08-01 03:56:53 +000014#include <asm/hardware.h>
15
16#define CONFIG_SYS_TEXT_BASE 0x21F00000
Jens Scharsig128ecd02010-02-03 22:45:42 +010017
Stelian Pop0bf5cad2008-05-08 18:52:25 +020018/* ARM asynchronous clock */
Xu, Hong0c0fb212011-08-01 03:56:53 +000019#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
20#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
Stelian Pop0bf5cad2008-05-08 18:52:25 +020021
Xu, Hong0c0fb212011-08-01 03:56:53 +000022#define CONFIG_AT91SAM9RLEK 1 /* It's an AT91SAM9RLEK Board */
23
Jean-Christophe PLAGNIOL-VILLARD23164f12009-04-16 21:30:44 +020024#define CONFIG_ARCH_CPU_INIT
Xu, Hong0c0fb212011-08-01 03:56:53 +000025#define CONFIG_SKIP_LOWLEVEL_INIT
26#define CONFIG_BOARD_EARLY_INIT_F
Stelian Pop0bf5cad2008-05-08 18:52:25 +020027
Xu, Hong0c0fb212011-08-01 03:56:53 +000028#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
29#define CONFIG_SETUP_MEMORY_TAGS 1
30#define CONFIG_INITRD_TAG 1
Stelian Pop0bf5cad2008-05-08 18:52:25 +020031
Xu, Hong0c0fb212011-08-01 03:56:53 +000032#define CONFIG_DISPLAY_CPUINFO
33
Nicolas Ferree4f36232013-02-20 00:16:24 +000034#define CONFIG_CMD_BOOTZ
Nicolas Ferre6ddbdb12013-02-20 00:16:23 +000035#define CONFIG_OF_LIBFDT
36
Wu, Joshef905732014-09-02 18:14:11 +080037#define CONFIG_SYS_GENERIC_BOARD
38
Xu, Hong0c0fb212011-08-01 03:56:53 +000039#define CONFIG_ATMEL_LEGACY
40#define CONFIG_AT91_GPIO 1
41#define CONFIG_AT91_GPIO_PULLUP 1
Stelian Pop0bf5cad2008-05-08 18:52:25 +020042
43/*
44 * Hardware drivers
45 */
Xu, Hong0c0fb212011-08-01 03:56:53 +000046
47/* serial console */
48#define CONFIG_ATMEL_USART
49#define CONFIG_USART_BASE ATMEL_BASE_DBGU
50#define CONFIG_USART_ID ATMEL_ID_SYS
51#define CONFIG_BAUDRATE 115200
Stelian Pop0bf5cad2008-05-08 18:52:25 +020052
Stelian Popcea5c532008-05-08 14:52:32 +020053/* LCD */
54#define CONFIG_LCD 1
55#define LCD_BPP LCD_COLOR8
56#define CONFIG_LCD_LOGO 1
57#undef LCD_TEST_PATTERN
58#define CONFIG_LCD_INFO 1
59#define CONFIG_LCD_INFO_BELOW_LOGO 1
Xu, Hong0c0fb212011-08-01 03:56:53 +000060#define CONFIG_SYS_WHITE_ON_BLACK 1
Stelian Popcea5c532008-05-08 14:52:32 +020061#define CONFIG_ATMEL_LCD 1
62#define CONFIG_ATMEL_LCD_RGB565 1
Xu, Hong0c0fb212011-08-01 03:56:53 +000063/* Let board_init_f handle the framebuffer allocation */
64#undef CONFIG_FB_ADDR
65#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
66
Stelian Popcea5c532008-05-08 14:52:32 +020067
Jean-Christophe PLAGNIOL-VILLARD476d10e2009-03-21 21:08:00 +010068/* LED */
69#define CONFIG_AT91_LED
70#define CONFIG_RED_LED AT91_PIN_PD14 /* this is the power led */
71#define CONFIG_GREEN_LED AT91_PIN_PD15 /* this is the user1 led */
72#define CONFIG_YELLOW_LED AT91_PIN_PD16 /* this is the user2 led */
73
Stelian Pop0bf5cad2008-05-08 18:52:25 +020074#define CONFIG_BOOTDELAY 3
75
Stelian Pop0bf5cad2008-05-08 18:52:25 +020076/*
77 * Command line configuration.
78 */
79#include <config_cmd_default.h>
80#undef CONFIG_CMD_BDI
Stelian Pop0bf5cad2008-05-08 18:52:25 +020081#undef CONFIG_CMD_FPGA
Wolfgang Denk85c25df2009-04-01 23:34:12 +020082#undef CONFIG_CMD_IMI
Stelian Pop0bf5cad2008-05-08 18:52:25 +020083#undef CONFIG_CMD_IMLS
Wolfgang Denk85c25df2009-04-01 23:34:12 +020084#undef CONFIG_CMD_LOADS
Stelian Pop0bf5cad2008-05-08 18:52:25 +020085#undef CONFIG_CMD_NET
Xu, Hong0c0fb212011-08-01 03:56:53 +000086#undef CONFIG_CMD_NFS
Wolfgang Denk85c25df2009-04-01 23:34:12 +020087#undef CONFIG_CMD_SOURCE
Stelian Pop0bf5cad2008-05-08 18:52:25 +020088#undef CONFIG_CMD_USB
89
Xu, Hong0c0fb212011-08-01 03:56:53 +000090#define CONFIG_CMD_NAND 1
Stelian Pop0bf5cad2008-05-08 18:52:25 +020091
92/* SDRAM */
93#define CONFIG_NR_DRAM_BANKS 1
Xu, Hong0c0fb212011-08-01 03:56:53 +000094#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
95#define CONFIG_SYS_SDRAM_SIZE 0x04000000
96
97#define CONFIG_SYS_INIT_SP_ADDR \
98 (ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)
Stelian Pop0bf5cad2008-05-08 18:52:25 +020099
100/* DataFlash */
Jean-Christophe PLAGNIOL-VILLARDe5437ac2009-03-27 23:26:44 +0100101#define CONFIG_ATMEL_DATAFLASH_SPI
Xu, Hong0c0fb212011-08-01 03:56:53 +0000102#define CONFIG_HAS_DATAFLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200103#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
104#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
105#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
Xu, Hong0c0fb212011-08-01 03:56:53 +0000106#define AT91_SPI_CLK 15000000
107#define DATAFLASH_TCSS (0x1a << 16)
108#define DATAFLASH_TCHS (0x1 << 24)
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200109
110/* NOR flash - not present */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200111#define CONFIG_SYS_NO_FLASH 1
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200112
113/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100114#ifdef CONFIG_CMD_NAND
115#define CONFIG_NAND_ATMEL
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_MAX_NAND_DEVICE 1
Xu, Hong0c0fb212011-08-01 03:56:53 +0000117#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200118#define CONFIG_SYS_NAND_DBW_8 1
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100119/* our ALE is AD21 */
120#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
121/* our CLE is AD22 */
122#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
123#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
124#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17
Wolfgang Denk1f797742009-07-18 21:52:24 +0200125
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100126#endif
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200127
128/* Ethernet - not present */
129
130/* USB - not supported */
131
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200132#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200133
Xu, Hong0c0fb212011-08-01 03:56:53 +0000134#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200135#define CONFIG_SYS_MEMTEST_END 0x23e00000
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200136
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137#ifdef CONFIG_SYS_USE_DATAFLASH
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200138
139/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Jean-Christophe PLAGNIOL-VILLARD2b14d2b2008-09-10 22:47:58 +0200140#define CONFIG_ENV_IS_IN_DATAFLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200141#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200142#define CONFIG_ENV_OFFSET 0x4200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200143#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200144#define CONFIG_ENV_SIZE 0x4200
Alexandre Belloni9ef19ba2012-07-02 04:26:58 +0000145#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm"
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200146#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
147 "root=/dev/mtdblock0 " \
Albin Tonnerreeaa6db22009-07-22 18:30:03 +0200148 "mtdparts=atmel_nand:-(root) "\
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200149 "rw rootfstype=jffs2"
150
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151#else /* CONFIG_SYS_USE_NANDFLASH */
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200152
153/* bootstrap + u-boot + env + linux in nandflash */
Xu, Hong0c0fb212011-08-01 03:56:53 +0000154#define CONFIG_ENV_IS_IN_NAND 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200155#define CONFIG_ENV_OFFSET 0x60000
156#define CONFIG_ENV_OFFSET_REDUND 0x80000
157#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200158#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
159#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
160 "root=/dev/mtdblock5 " \
Albin Tonnerreeaa6db22009-07-22 18:30:03 +0200161 "mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200162 "rw rootfstype=jffs2"
163
164#endif
165
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200166#define CONFIG_SYS_PROMPT "U-Boot> "
167#define CONFIG_SYS_CBSIZE 256
168#define CONFIG_SYS_MAXARGS 16
169#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
170#define CONFIG_SYS_LONGHELP 1
Xu, Hong0c0fb212011-08-01 03:56:53 +0000171#define CONFIG_CMDLINE_EDITING 1
Alexandre Belloni9ef19ba2012-07-02 04:26:58 +0000172#define CONFIG_AUTO_COMPLETE
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200173
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200174/*
175 * Size of malloc() pool
176 */
Xu, Hong0c0fb212011-08-01 03:56:53 +0000177#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200178
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200179#endif