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git01.mediatek.com / filogic / uboot / 0f33ef24990ed9fcf6d7c29e177902c10f95a41b / . / arch / arm / dts / imx8mp-rsb3720-a1.dts
blob: 2d8dc1964736a5a5cdc11ec230309798de66af4c [file] [log] [blame]
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 * Copyright 2022 Linaro
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/usb/pd.h>
10#include "imx8mp.dtsi"
11
12/ {
13 model = "Advantech i.MX8MPlus RSB3720A1 board";
14 compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
15
16 aliases {
17 rtc0 = &s35390a;
18 rtc1 = &snvs_rtc;
19 };
20
21 chosen {
22 stdout-path = &uart3;
23 };
24
25 memory@40000000 {
26 device_type = "memory";
27 reg = <0x0 0x40000000 0 0xc0000000>,
28 <0x1 0x00000000 0 0xc0000000>;
29 };
30
31 reserved-memory {
32 #address-cells = <2>;
33 #size-cells = <2>;
34 ranges;
35
36 rpmsg_reserved: rpmsg@0x55800000 {
37 no-map;
38 reg = <0 0x55800000 0 0x800000>;
39 };
40 };
41
42 leds {
43 compatible = "gpio-leds";
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_gpio_led>;
46
47 user {
48 label = "user";
49 gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
50 default-state = "off"; /* LED BLUE */
51 };
52 };
53
54 reg_usb1_host_vbus: regulator-usb1-vbus {
55 compatible = "regulator-fixed";
56 regulator-name = "usb1_host_vbus";
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_usb1_vbus>;
59 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <5000000>;
61 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
62 enable-active-high;
63 regulator-always-on;
64 };
65
66 reg_usdhc1_vmmc: regulator-usdhc1 {
67 compatible = "regulator-fixed";
68 regulator-name = "WLAN_EN";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71 gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
72 enable-active-high;
73 startup-delay-us = <100>;
74 off-on-delay-us = <12000>;
75 };
76
77 reg_usdhc2_vmmc: regulator-usdhc2 {
78 compatible = "regulator-fixed";
79 regulator-name = "VSD_3V3";
80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>;
82 //gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
83 enable-active-high;
84 startup-delay-us = <100>;
85 off-on-delay-us = <12000>;
86 };
87
88 lvds_backlight0: lvds_backlight@0 {
89 compatible = "pwm-backlight";
90 pwms = <&pwm2 0 5000000>;
91 status = "disabled";
92
93 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
94 10 11 12 13 14 15 16 17 18 19
95 20 21 22 23 24 25 26 27 28 29
96 30 31 32 33 34 35 36 37 38 39
97 40 41 42 43 44 45 46 47 48 49
98 50 51 52 53 54 55 56 57 58 59
99 60 61 62 63 64 65 66 67 68 69
100 70 71 72 73 74 75 76 77 78 79
101 80 81 82 83 84 85 86 87 88 89
102 90 91 92 93 94 95 96 97 98 99
103 100>;
104 default-brightness-level = <80>;
105 };
106
107 lvds_backlight1: lvds_backlight@1 {
108 compatible = "pwm-backlight";
109 pwms = <&pwm3 0 5000000>;
110 status = "disabled";
111
112 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
113 10 11 12 13 14 15 16 17 18 19
114 20 21 22 23 24 25 26 27 28 29
115 30 31 32 33 34 35 36 37 38 39
116 40 41 42 43 44 45 46 47 48 49
117 50 51 52 53 54 55 56 57 58 59
118 60 61 62 63 64 65 66 67 68 69
119 70 71 72 73 74 75 76 77 78 79
120 80 81 82 83 84 85 86 87 88 89
121 90 91 92 93 94 95 96 97 98 99
122 100>;
123 default-brightness-level = <80>;
124 };
125
126 rtl8367 {
127 compatible = "realtek,rtl8367b";
128 pinctrl-names = "default";
129 gpio-sda = <&gpio5 10 GPIO_ACTIVE_HIGH>;
130 gpio-sck = <&gpio5 11 GPIO_ACTIVE_HIGH>;
131 realtek,extif0 = <1 0 1 1 1 1 1 1 2>;
132 };
133};
134
135&clk {
136 init-on-array = <IMX8MP_CLK_HSIO_ROOT>;
137};
138
139&A53_0 {
140 cpu-supply = <&buck2_reg>;
141};
142
143&pwm2 {
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_pwm2>;
Marcel Ziswileradce5052022-07-21 15:45:26 +0200[diff] [blame]146 #pwm-cells = <2>;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]147 status = "okay";
148};
149
150&pwm3 {
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_pwm3>;
Marcel Ziswileradce5052022-07-21 15:45:26 +0200[diff] [blame]153 #pwm-cells = <2>;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]154 status = "okay";
155};
156
157&fec {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_fec>;
160 phy-mode = "rgmii-id";
161 phy-handle = <&ethphy1>;
162 fsl,magic-packet;
163 status = "okay";
164
165 mdio {
166 #address-cells = <1>;
167 #size-cells = <0>;
168
169 ethphy1: ethernet-phy@4 {
170 compatible = "ethernet-phy-ieee802.3-c22";
171 reg = <4>;
172 at803x,eee-disabled;
173 at803x,vddio-1p8v;
174 };
175 };
176};
177
178&i2c1 {
179 clock-frequency = <100000>;
180 pinctrl-names = "default", "gpio";
181 pinctrl-0 = <&pinctrl_i2c1>;
182 pinctrl-1 = <&pinctrl_i2c1_gpio>;
183 scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
184 sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
185 status = "okay";
186
187 pmic: pca9450@25 {
188 reg = <0x25>;
189 compatible = "nxp,pca9450c", "nxp,pca9450b", "nxp,pca9450";
190 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
191 pinctrl-0 = <&pinctrl_pmic>;
192 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
193
194 regulators {
195 #address-cells = <1>;
196 #size-cells = <0>;
197
198 pca9450,pmic-buck2-uses-i2c-dvs;
199 /* Run/Standby voltage */
200 pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
201
202 buck1_reg: regulator@0 {
203 reg = <0>;
204 regulator-compatible = "buck1";
205 regulator-min-microvolt = <600000>;
206 regulator-max-microvolt = <2187500>;
207 regulator-boot-on;
208 regulator-always-on;
209 regulator-ramp-delay = <3125>;
210 };
211
212 buck2_reg: regulator@1 {
213 reg = <1>;
214 regulator-compatible = "buck2";
215 regulator-min-microvolt = <600000>;
216 regulator-max-microvolt = <2187500>;
217 regulator-boot-on;
218 regulator-always-on;
219 regulator-ramp-delay = <3125>;
220 };
221
222 buck4_reg: regulator@3 {
223 reg = <3>;
224 regulator-compatible = "buck4";
225 regulator-min-microvolt = <600000>;
226 regulator-max-microvolt = <3400000>;
227 regulator-boot-on;
228 regulator-always-on;
229 };
230
231 buck5_reg: regulator@4 {
232 reg = <4>;
233 regulator-compatible = "buck5";
234 regulator-min-microvolt = <600000>;
235 regulator-max-microvolt = <3400000>;
236 regulator-boot-on;
237 regulator-always-on;
238 };
239
240 buck6_reg: regulator@5 {
241 reg = <5>;
242 regulator-compatible = "buck6";
243 regulator-min-microvolt = <600000>;
244 regulator-max-microvolt = <3400000>;
245 regulator-boot-on;
246 regulator-always-on;
247 };
248
249 ldo1_reg: regulator@6 {
250 reg = <6>;
251 regulator-compatible = "ldo1";
252 regulator-min-microvolt = <1600000>;
253 regulator-max-microvolt = <3300000>;
254 regulator-boot-on;
255 regulator-always-on;
256 };
257
258 ldo2_reg: regulator@7 {
259 reg = <7>;
260 regulator-compatible = "ldo2";
261 regulator-min-microvolt = <800000>;
262 regulator-max-microvolt = <1150000>;
263 regulator-boot-on;
264 regulator-always-on;
265 };
266
267 ldo3_reg: regulator@8 {
268 reg = <8>;
269 regulator-compatible = "ldo3";
270 regulator-min-microvolt = <800000>;
271 regulator-max-microvolt = <3300000>;
272 regulator-boot-on;
273 regulator-always-on;
274 };
275
276 ldo4_reg: regulator@9 {
277 reg = <9>;
278 regulator-compatible = "ldo4";
279 regulator-min-microvolt = <800000>;
280 regulator-max-microvolt = <3300000>;
281 regulator-boot-on;
282 regulator-always-on;
283 };
284
285 ldo5_reg: regulator@10 {
286 reg = <10>;
287 regulator-compatible = "ldo5";
288 regulator-min-microvolt = <1800000>;
289 regulator-max-microvolt = <3300000>;
290 };
291 };
292 };
293
294 s35390a: s35390a@30 {
295 compatible = "sii,s35390a", "sii,s35392a";
296 reg = <0x30>;
297 status = "okay";
298 };
299
300 gpio_exp2: tca9538@71 {
301 compatible = "nxp,pca9538";
302 reg = <0x71>;
303 gpio-controller;
304 #gpio-cells = <2>;
305 };
306
307 gpio_exp1: tca9538@70 {
308 compatible = "nxp,pca9538";
309 reg = <0x70>;
310 gpio-controller;
311 #gpio-cells = <2>;
312 };
313};
314
315&i2c2 {
316 clock-frequency = <100000>;
317 pinctrl-names = "default", "gpio";
318 pinctrl-0 = <&pinctrl_i2c2>;
319 pinctrl-1 = <&pinctrl_i2c2_gpio>;
320 scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
321 sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
322 status = "okay";
323};
324
325&i2c3 {
326 clock-frequency = <100000>;
327 pinctrl-names = "default", "gpio";
328 pinctrl-0 = <&pinctrl_i2c3>;
329 pinctrl-1 = <&pinctrl_i2c3_gpio>;
330 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
331 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
332 status = "okay";
333
334 pca6416: gpio@20 {
335 compatible = "ti,tca6416";
336 reg = <0x20>;
337 gpio-controller;
338 #gpio-cells = <2>;
339 };
340};
341
342&i2c4 {
343 clock-frequency = <100000>;
344 pinctrl-names = "default", "gpio";
345 pinctrl-0 = <&pinctrl_i2c4>;
346 pinctrl-1 = <&pinctrl_i2c4_gpio>;
347 scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
348 sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
349 status = "okay";
350
351 24c02@50 {
352 compatible = "fsl,24c02";
353 reg = <0x50>;
354 };
355};
356
357&snvs_pwrkey {
358 status = "okay";
359};
360
361&flexcan1 {
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_flexcan1>;
364 status = "okay";
365};
366
367&flexcan2 {
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_flexcan2>;
370 status = "okay";
371};
372
373&uart1 { /* BT */
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_uart1>;
376 assigned-clocks = <&clk IMX8MP_CLK_UART1>;
377 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
378 fsl,uart-has-rtscts;
379 status = "okay";
380};
381
382&uart2 {
383 pinctrl-names = "default";
384 pinctrl-0 = <&pinctrl_uart2>;
385 status = "okay";
386};
387
388&uart3 {
389 /* console */
390 pinctrl-names = "default";
391 pinctrl-0 = <&pinctrl_uart3>;
392 assigned-clocks = <&clk IMX8MP_CLK_UART3>;
393 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
394 fsl,uart-has-rtscts;
395 status = "okay";
396};
397
398&uart4 {
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_uart4>;
401 status = "okay";
402};
403
404&usb3_phy0 {
405 fsl,phy-tx-vref-tune = <6>;
406 fsl,phy-tx-rise-tune = <0>;
407 fsl,phy-tx-preemp-amp-tune = <3>;
408 fsl,phy-comp-dis-tune = <7>;
409 fsl,pcs-tx-deemph-3p5db = <0x21>;
410 fsl,phy-pcs-tx-swing-full = <0x7f>;
411 status = "okay";
412};
413
414&usb3_0 {
415 status = "okay";
416};
417
418&usb_dwc3_0 {
419 dr_mode = "host";
420 status = "okay";
421};
422
423&usb3_phy1 {
424 fsl,phy-tx-preemp-amp-tune = <2>;
425 status = "okay";
426};
427
428&usb3_1 {
429 status = "okay";
430};
431
432&usb_dwc3_1 {
433 dr_mode = "host";
434 status = "okay";
435};
436
437&usdhc2 {
438 pinctrl-names = "default", "state_100mhz", "state_200mhz";
439 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
440 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
441 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
442 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
443 vmmc-supply = <&reg_usdhc2_vmmc>;
444 bus-width = <4>;
445 status = "okay";
446};
447
448&usdhc3 {
449 pinctrl-names = "default", "state_100mhz", "state_200mhz";
450 pinctrl-0 = <&pinctrl_usdhc3>;
451 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
452 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
453 bus-width = <8>;
454 cqe-disabled;
455 non-removable;
456 status = "okay";
457};
458
459&wdog1 {
460 pinctrl-names = "default";
461 pinctrl-0 = <&pinctrl_wdog>;
462 fsl,ext-reset-output;
463 status = "disabled";
464};
465
466&iomuxc {
467 pinctrl-names = "default";
468
469 pinctrl_pwm2: pwm2grp {
470 fsl,pins = <
471 MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116
472 >;
473 };
474
475 pinctrl_pwm3: pwm3grp {
476 fsl,pins = <
477 MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x116
478 >;
479 };
480
481 pinctrl_eqos: eqosgrp {
482 fsl,pins = <
483 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
484 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
485 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
486 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
487 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
488 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
489 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
490 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
491 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
492 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
493 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
494 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
495 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
496 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
497 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
498 >;
499 };
500
501 pinctrl_fec: fecgrp {
502 fsl,pins = <
503 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
504 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
505 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
506 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
507 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
508 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
509 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
510 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
511 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
512 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
513 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
514 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
515 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
516 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
517 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
518 >;
519 };
520
521 pinctrl_flexcan1: flexcan1grp {
522 fsl,pins = <
523 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
524 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
525 >;
526 };
527
528 pinctrl_flexcan2: flexcan2grp {
529 fsl,pins = <
530 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
531 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
532 >;
533 };
534
535 pinctrl_flexspi0: flexspi0grp {
536 fsl,pins = <
537 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
538 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
539 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
540 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
541 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
542 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
543 >;
544 };
545
546 pinctrl_gpio_led: gpioledgrp {
547 fsl,pins = <
548 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x19
549 >;
550 };
551
552 pinctrl_i2c1: i2c1grp {
553 fsl,pins = <
554 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
555 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
556 >;
557 };
558
559 pinctrl_i2c2: i2c2grp {
560 fsl,pins = <
561 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
562 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
563 >;
564 };
565
566 pinctrl_i2c3: i2c3grp {
567 fsl,pins = <
568 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
569 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
570 >;
571 };
572
573 pinctrl_i2c4: i2c4grp {
574 fsl,pins = <
575 MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x400001c3
576 MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x400001c3
577 >;
578 };
579
580 pinctrl_i2c1_gpio: i2c1grp-gpio {
581 fsl,pins = <
582 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
583 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
584 >;
585 };
586
587 pinctrl_i2c2_gpio: i2c2grp-gpio {
588 fsl,pins = <
589 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3
590 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3
591 >;
592 };
593
594 pinctrl_i2c3_gpio: i2c3grp-gpio {
595 fsl,pins = <
596 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3
597 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3
598 >;
599 };
600
601 pinctrl_i2c4_gpio: i2c4_gpio_grp {
602 fsl,pins = <
603 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3
604 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3
605 >;
606 };
607
608 pinctrl_pmic: pmicirq {
609 fsl,pins = <
610 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
611 >;
612 };
613
614 pinctrl_sai2: sai2grp {
615 fsl,pins = <
616 MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
617 MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
618 MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
619 MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
620 >;
621 };
622
623 pinctrl_sai3: sai3grp {
624 fsl,pins = <
625 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
626 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
627 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
628 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
629 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
630 >;
631 };
632
633 pinctrl_uart1: uart1grp {
634 fsl,pins = <
635 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
636 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
637 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
638 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
639 >;
640 };
641
642 pinctrl_uart2: uart2grp {
643 fsl,pins = <
644 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
645 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
646 >;
647 };
648
649 pinctrl_uart3: uart3grp {
650 fsl,pins = <
651 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
652 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
653 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
654 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
655 >;
656 };
657
658 pinctrl_uart4: uart4grp {
659 fsl,pins = <
660 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
661 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
662 >;
663 };
664
665 pinctrl_usb1_vbus: usb1grp {
666 fsl,pins = <
667 MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19
668 >;
669 };
670
671 pinctrl_usdhc1: usdhc1grp {
672 fsl,pins = <
673 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
674 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
675 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
676 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
677 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
678 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
679 >;
680 };
681
682 pinctrl_usdhc1_gpio: usdhc1gpiogrp {
683 fsl,pins = <
684 MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x19
685 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x19
686 >;
687 };
688
689 pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
690 fsl,pins = <
691 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
692 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
693 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
694 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
695 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
696 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
697 >;
698 };
699
700 pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
701 fsl,pins = <
702 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
703 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
704 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
705 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
706 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
707 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
708 >;
709 };
710
711 pinctrl_usdhc2: usdhc2grp {
712 fsl,pins = <
713 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
714 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
715 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
716 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
717 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
718 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
719 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
720 >;
721 };
722
723 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
724 fsl,pins = <
725 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
726 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
727 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
728 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
729 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
730 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
731 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
732 >;
733 };
734
735 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
736 fsl,pins = <
737 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
738 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
739 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
740 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
741 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
742 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
743 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
744 >;
745 };
746
747 pinctrl_usdhc2_gpio: usdhc2grp-gpio {
748 fsl,pins = <
749 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
750 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
751 >;
752 };
753
754 pinctrl_usdhc3: usdhc3grp {
755 fsl,pins = <
756 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
757 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
758 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
759 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
760 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
761 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
762 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
763 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
764 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
765 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
766 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
767 >;
768 };
769
770 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
771 fsl,pins = <
772 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
773 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
774 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
775 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
776 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
777 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
778 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
779 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
780 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
781 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
782 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
783 >;
784 };
785
786 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
787 fsl,pins = <
788 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
789 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
790 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
791 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
792 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
793 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
794 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
795 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
796 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
797 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
798 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
799 >;
800 };
801
802 pinctrl_wdog: wdoggrp {
803 fsl,pins = <
804 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
805 >;
806 };
807};