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git01.mediatek.com / filogic / uboot / f183f1328a588efb20a30e322a76f7ec33d44cd4 / . / arch / arm / dts / imx8mp-rsb3720-a1.dts
blob: 1ef1c0c99efdb44e5d5464e41a05132b38377f17 [file] [log] [blame]
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 * Copyright 2022 Linaro
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/usb/pd.h>
10#include "imx8mp.dtsi"
11
12/ {
13 model = "Advantech i.MX8MPlus RSB3720A1 board";
14 compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
15
16 aliases {
17 rtc0 = &s35390a;
18 rtc1 = &snvs_rtc;
19 };
20
21 chosen {
22 stdout-path = &uart3;
23 };
24
25 memory@40000000 {
26 device_type = "memory";
27 reg = <0x0 0x40000000 0 0xc0000000>,
28 <0x1 0x00000000 0 0xc0000000>;
29 };
30
31 reserved-memory {
32 #address-cells = <2>;
33 #size-cells = <2>;
34 ranges;
35
36 rpmsg_reserved: rpmsg@0x55800000 {
37 no-map;
38 reg = <0 0x55800000 0 0x800000>;
39 };
40 };
41
42 leds {
43 compatible = "gpio-leds";
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_gpio_led>;
46
47 user {
48 label = "user";
49 gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
50 default-state = "off"; /* LED BLUE */
51 };
52 };
53
54 reg_usb1_host_vbus: regulator-usb1-vbus {
55 compatible = "regulator-fixed";
56 regulator-name = "usb1_host_vbus";
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_usb1_vbus>;
59 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <5000000>;
61 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
62 enable-active-high;
63 regulator-always-on;
64 };
65
66 reg_usdhc1_vmmc: regulator-usdhc1 {
67 compatible = "regulator-fixed";
68 regulator-name = "WLAN_EN";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71 gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
72 enable-active-high;
73 startup-delay-us = <100>;
74 off-on-delay-us = <12000>;
75 };
76
77 reg_usdhc2_vmmc: regulator-usdhc2 {
78 compatible = "regulator-fixed";
79 regulator-name = "VSD_3V3";
80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>;
82 //gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
83 enable-active-high;
84 startup-delay-us = <100>;
85 off-on-delay-us = <12000>;
86 };
87
88 lvds_backlight0: lvds_backlight@0 {
89 compatible = "pwm-backlight";
90 pwms = <&pwm2 0 5000000>;
91 status = "disabled";
92
93 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
94 10 11 12 13 14 15 16 17 18 19
95 20 21 22 23 24 25 26 27 28 29
96 30 31 32 33 34 35 36 37 38 39
97 40 41 42 43 44 45 46 47 48 49
98 50 51 52 53 54 55 56 57 58 59
99 60 61 62 63 64 65 66 67 68 69
100 70 71 72 73 74 75 76 77 78 79
101 80 81 82 83 84 85 86 87 88 89
102 90 91 92 93 94 95 96 97 98 99
103 100>;
104 default-brightness-level = <80>;
105 };
106
107 lvds_backlight1: lvds_backlight@1 {
108 compatible = "pwm-backlight";
109 pwms = <&pwm3 0 5000000>;
110 status = "disabled";
111
112 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
113 10 11 12 13 14 15 16 17 18 19
114 20 21 22 23 24 25 26 27 28 29
115 30 31 32 33 34 35 36 37 38 39
116 40 41 42 43 44 45 46 47 48 49
117 50 51 52 53 54 55 56 57 58 59
118 60 61 62 63 64 65 66 67 68 69
119 70 71 72 73 74 75 76 77 78 79
120 80 81 82 83 84 85 86 87 88 89
121 90 91 92 93 94 95 96 97 98 99
122 100>;
123 default-brightness-level = <80>;
124 };
125
126 rtl8367 {
127 compatible = "realtek,rtl8367b";
128 pinctrl-names = "default";
129 gpio-sda = <&gpio5 10 GPIO_ACTIVE_HIGH>;
130 gpio-sck = <&gpio5 11 GPIO_ACTIVE_HIGH>;
131 realtek,extif0 = <1 0 1 1 1 1 1 1 2>;
132 };
133};
134
135&clk {
136 init-on-array = <IMX8MP_CLK_HSIO_ROOT>;
137};
138
139&A53_0 {
140 cpu-supply = <&buck2_reg>;
141};
142
143&pwm2 {
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_pwm2>;
146 status = "okay";
147};
148
149&pwm3 {
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_pwm3>;
152 status = "okay";
153};
154
155&fec {
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_fec>;
158 phy-mode = "rgmii-id";
159 phy-handle = <&ethphy1>;
160 fsl,magic-packet;
161 status = "okay";
162
163 mdio {
164 #address-cells = <1>;
165 #size-cells = <0>;
166
167 ethphy1: ethernet-phy@4 {
168 compatible = "ethernet-phy-ieee802.3-c22";
169 reg = <4>;
170 at803x,eee-disabled;
171 at803x,vddio-1p8v;
172 };
173 };
174};
175
176&i2c1 {
177 clock-frequency = <100000>;
178 pinctrl-names = "default", "gpio";
179 pinctrl-0 = <&pinctrl_i2c1>;
180 pinctrl-1 = <&pinctrl_i2c1_gpio>;
181 scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
182 sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
183 status = "okay";
184
185 pmic: pca9450@25 {
186 reg = <0x25>;
187 compatible = "nxp,pca9450c", "nxp,pca9450b", "nxp,pca9450";
188 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
189 pinctrl-0 = <&pinctrl_pmic>;
190 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
191
192 regulators {
193 #address-cells = <1>;
194 #size-cells = <0>;
195
196 pca9450,pmic-buck2-uses-i2c-dvs;
197 /* Run/Standby voltage */
198 pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
199
200 buck1_reg: regulator@0 {
201 reg = <0>;
202 regulator-compatible = "buck1";
203 regulator-min-microvolt = <600000>;
204 regulator-max-microvolt = <2187500>;
205 regulator-boot-on;
206 regulator-always-on;
207 regulator-ramp-delay = <3125>;
208 };
209
210 buck2_reg: regulator@1 {
211 reg = <1>;
212 regulator-compatible = "buck2";
213 regulator-min-microvolt = <600000>;
214 regulator-max-microvolt = <2187500>;
215 regulator-boot-on;
216 regulator-always-on;
217 regulator-ramp-delay = <3125>;
218 };
219
220 buck4_reg: regulator@3 {
221 reg = <3>;
222 regulator-compatible = "buck4";
223 regulator-min-microvolt = <600000>;
224 regulator-max-microvolt = <3400000>;
225 regulator-boot-on;
226 regulator-always-on;
227 };
228
229 buck5_reg: regulator@4 {
230 reg = <4>;
231 regulator-compatible = "buck5";
232 regulator-min-microvolt = <600000>;
233 regulator-max-microvolt = <3400000>;
234 regulator-boot-on;
235 regulator-always-on;
236 };
237
238 buck6_reg: regulator@5 {
239 reg = <5>;
240 regulator-compatible = "buck6";
241 regulator-min-microvolt = <600000>;
242 regulator-max-microvolt = <3400000>;
243 regulator-boot-on;
244 regulator-always-on;
245 };
246
247 ldo1_reg: regulator@6 {
248 reg = <6>;
249 regulator-compatible = "ldo1";
250 regulator-min-microvolt = <1600000>;
251 regulator-max-microvolt = <3300000>;
252 regulator-boot-on;
253 regulator-always-on;
254 };
255
256 ldo2_reg: regulator@7 {
257 reg = <7>;
258 regulator-compatible = "ldo2";
259 regulator-min-microvolt = <800000>;
260 regulator-max-microvolt = <1150000>;
261 regulator-boot-on;
262 regulator-always-on;
263 };
264
265 ldo3_reg: regulator@8 {
266 reg = <8>;
267 regulator-compatible = "ldo3";
268 regulator-min-microvolt = <800000>;
269 regulator-max-microvolt = <3300000>;
270 regulator-boot-on;
271 regulator-always-on;
272 };
273
274 ldo4_reg: regulator@9 {
275 reg = <9>;
276 regulator-compatible = "ldo4";
277 regulator-min-microvolt = <800000>;
278 regulator-max-microvolt = <3300000>;
279 regulator-boot-on;
280 regulator-always-on;
281 };
282
283 ldo5_reg: regulator@10 {
284 reg = <10>;
285 regulator-compatible = "ldo5";
286 regulator-min-microvolt = <1800000>;
287 regulator-max-microvolt = <3300000>;
288 };
289 };
290 };
291
292 s35390a: s35390a@30 {
293 compatible = "sii,s35390a", "sii,s35392a";
294 reg = <0x30>;
295 status = "okay";
296 };
297
298 gpio_exp2: tca9538@71 {
299 compatible = "nxp,pca9538";
300 reg = <0x71>;
301 gpio-controller;
302 #gpio-cells = <2>;
303 };
304
305 gpio_exp1: tca9538@70 {
306 compatible = "nxp,pca9538";
307 reg = <0x70>;
308 gpio-controller;
309 #gpio-cells = <2>;
310 };
311};
312
313&i2c2 {
314 clock-frequency = <100000>;
315 pinctrl-names = "default", "gpio";
316 pinctrl-0 = <&pinctrl_i2c2>;
317 pinctrl-1 = <&pinctrl_i2c2_gpio>;
318 scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
319 sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
320 status = "okay";
321};
322
323&i2c3 {
324 clock-frequency = <100000>;
325 pinctrl-names = "default", "gpio";
326 pinctrl-0 = <&pinctrl_i2c3>;
327 pinctrl-1 = <&pinctrl_i2c3_gpio>;
328 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
329 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
330 status = "okay";
331
332 pca6416: gpio@20 {
333 compatible = "ti,tca6416";
334 reg = <0x20>;
335 gpio-controller;
336 #gpio-cells = <2>;
337 };
338};
339
340&i2c4 {
341 clock-frequency = <100000>;
342 pinctrl-names = "default", "gpio";
343 pinctrl-0 = <&pinctrl_i2c4>;
344 pinctrl-1 = <&pinctrl_i2c4_gpio>;
345 scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
346 sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
347 status = "okay";
348
349 24c02@50 {
350 compatible = "fsl,24c02";
351 reg = <0x50>;
352 };
353};
354
355&snvs_pwrkey {
356 status = "okay";
357};
358
359&flexcan1 {
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_flexcan1>;
362 status = "okay";
363};
364
365&flexcan2 {
366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_flexcan2>;
368 status = "okay";
369};
370
371&uart1 { /* BT */
372 pinctrl-names = "default";
373 pinctrl-0 = <&pinctrl_uart1>;
374 assigned-clocks = <&clk IMX8MP_CLK_UART1>;
375 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
376 fsl,uart-has-rtscts;
377 status = "okay";
378};
379
380&uart2 {
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_uart2>;
383 status = "okay";
384};
385
386&uart3 {
387 /* console */
388 pinctrl-names = "default";
389 pinctrl-0 = <&pinctrl_uart3>;
390 assigned-clocks = <&clk IMX8MP_CLK_UART3>;
391 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
392 fsl,uart-has-rtscts;
393 status = "okay";
394};
395
396&uart4 {
397 pinctrl-names = "default";
398 pinctrl-0 = <&pinctrl_uart4>;
399 status = "okay";
400};
401
402&usb3_phy0 {
403 fsl,phy-tx-vref-tune = <6>;
404 fsl,phy-tx-rise-tune = <0>;
405 fsl,phy-tx-preemp-amp-tune = <3>;
406 fsl,phy-comp-dis-tune = <7>;
407 fsl,pcs-tx-deemph-3p5db = <0x21>;
408 fsl,phy-pcs-tx-swing-full = <0x7f>;
409 status = "okay";
410};
411
412&usb3_0 {
413 status = "okay";
414};
415
416&usb_dwc3_0 {
417 dr_mode = "host";
418 status = "okay";
419};
420
421&usb3_phy1 {
422 fsl,phy-tx-preemp-amp-tune = <2>;
423 status = "okay";
424};
425
426&usb3_1 {
427 status = "okay";
428};
429
430&usb_dwc3_1 {
431 dr_mode = "host";
432 status = "okay";
433};
434
435&usdhc2 {
436 pinctrl-names = "default", "state_100mhz", "state_200mhz";
437 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
438 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
439 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
440 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
441 vmmc-supply = <&reg_usdhc2_vmmc>;
442 bus-width = <4>;
443 status = "okay";
444};
445
446&usdhc3 {
447 pinctrl-names = "default", "state_100mhz", "state_200mhz";
448 pinctrl-0 = <&pinctrl_usdhc3>;
449 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
450 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
451 bus-width = <8>;
452 cqe-disabled;
453 non-removable;
454 status = "okay";
455};
456
457&wdog1 {
458 pinctrl-names = "default";
459 pinctrl-0 = <&pinctrl_wdog>;
460 fsl,ext-reset-output;
461 status = "disabled";
462};
463
464&iomuxc {
465 pinctrl-names = "default";
466
467 pinctrl_pwm2: pwm2grp {
468 fsl,pins = <
469 MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116
470 >;
471 };
472
473 pinctrl_pwm3: pwm3grp {
474 fsl,pins = <
475 MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x116
476 >;
477 };
478
479 pinctrl_eqos: eqosgrp {
480 fsl,pins = <
481 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
482 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
483 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
484 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
485 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
486 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
487 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
488 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
489 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
490 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
491 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
492 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
493 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
494 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
495 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
496 >;
497 };
498
499 pinctrl_fec: fecgrp {
500 fsl,pins = <
501 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
502 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
503 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
504 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
505 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
506 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
507 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
508 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
509 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
510 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
511 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
512 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
513 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
514 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
515 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
516 >;
517 };
518
519 pinctrl_flexcan1: flexcan1grp {
520 fsl,pins = <
521 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
522 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
523 >;
524 };
525
526 pinctrl_flexcan2: flexcan2grp {
527 fsl,pins = <
528 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
529 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
530 >;
531 };
532
533 pinctrl_flexspi0: flexspi0grp {
534 fsl,pins = <
535 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
536 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
537 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
538 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
539 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
540 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
541 >;
542 };
543
544 pinctrl_gpio_led: gpioledgrp {
545 fsl,pins = <
546 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x19
547 >;
548 };
549
550 pinctrl_i2c1: i2c1grp {
551 fsl,pins = <
552 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
553 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
554 >;
555 };
556
557 pinctrl_i2c2: i2c2grp {
558 fsl,pins = <
559 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
560 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
561 >;
562 };
563
564 pinctrl_i2c3: i2c3grp {
565 fsl,pins = <
566 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
567 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
568 >;
569 };
570
571 pinctrl_i2c4: i2c4grp {
572 fsl,pins = <
573 MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x400001c3
574 MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x400001c3
575 >;
576 };
577
578 pinctrl_i2c1_gpio: i2c1grp-gpio {
579 fsl,pins = <
580 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
581 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
582 >;
583 };
584
585 pinctrl_i2c2_gpio: i2c2grp-gpio {
586 fsl,pins = <
587 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3
588 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3
589 >;
590 };
591
592 pinctrl_i2c3_gpio: i2c3grp-gpio {
593 fsl,pins = <
594 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3
595 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3
596 >;
597 };
598
599 pinctrl_i2c4_gpio: i2c4_gpio_grp {
600 fsl,pins = <
601 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3
602 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3
603 >;
604 };
605
606 pinctrl_pmic: pmicirq {
607 fsl,pins = <
608 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
609 >;
610 };
611
612 pinctrl_sai2: sai2grp {
613 fsl,pins = <
614 MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
615 MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
616 MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
617 MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
618 >;
619 };
620
621 pinctrl_sai3: sai3grp {
622 fsl,pins = <
623 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
624 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
625 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
626 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
627 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
628 >;
629 };
630
631 pinctrl_uart1: uart1grp {
632 fsl,pins = <
633 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
634 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
635 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
636 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
637 >;
638 };
639
640 pinctrl_uart2: uart2grp {
641 fsl,pins = <
642 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
643 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
644 >;
645 };
646
647 pinctrl_uart3: uart3grp {
648 fsl,pins = <
649 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
650 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
651 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
652 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
653 >;
654 };
655
656 pinctrl_uart4: uart4grp {
657 fsl,pins = <
658 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
659 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
660 >;
661 };
662
663 pinctrl_usb1_vbus: usb1grp {
664 fsl,pins = <
665 MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19
666 >;
667 };
668
669 pinctrl_usdhc1: usdhc1grp {
670 fsl,pins = <
671 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
672 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
673 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
674 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
675 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
676 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
677 >;
678 };
679
680 pinctrl_usdhc1_gpio: usdhc1gpiogrp {
681 fsl,pins = <
682 MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x19
683 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x19
684 >;
685 };
686
687 pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
688 fsl,pins = <
689 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
690 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
691 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
692 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
693 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
694 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
695 >;
696 };
697
698 pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
699 fsl,pins = <
700 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
701 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
702 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
703 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
704 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
705 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
706 >;
707 };
708
709 pinctrl_usdhc2: usdhc2grp {
710 fsl,pins = <
711 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
712 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
713 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
714 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
715 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
716 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
717 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
718 >;
719 };
720
721 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
722 fsl,pins = <
723 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
724 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
725 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
726 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
727 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
728 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
729 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
730 >;
731 };
732
733 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
734 fsl,pins = <
735 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
736 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
737 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
738 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
739 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
740 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
741 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
742 >;
743 };
744
745 pinctrl_usdhc2_gpio: usdhc2grp-gpio {
746 fsl,pins = <
747 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
748 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
749 >;
750 };
751
752 pinctrl_usdhc3: usdhc3grp {
753 fsl,pins = <
754 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
755 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
756 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
757 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
758 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
759 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
760 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
761 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
762 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
763 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
764 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
765 >;
766 };
767
768 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
769 fsl,pins = <
770 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
771 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
772 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
773 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
774 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
775 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
776 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
777 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
778 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
779 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
780 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
781 >;
782 };
783
784 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
785 fsl,pins = <
786 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
787 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
788 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
789 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
790 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
791 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
792 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
793 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
794 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
795 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
796 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
797 >;
798 };
799
800 pinctrl_wdog: wdoggrp {
801 fsl,pins = <
802 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
803 >;
804 };
805};