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git01.mediatek.com / filogic / uboot / 0ef03ac7c65ece1ac5a9d88f99601157726d78e8 / . / arch / arm / dts / imx93-11x11-evk-u-boot.dtsi
blob: a99ba99bfb4f2c08752472536f2450c8e79fb87e [file] [log] [blame]
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2022 NXP
4 */
5
Mathieu Othacehe0ef03ac2024-01-04 16:30:09 +0100[diff] [blame^]6#include "imx93-u-boot.dtsi"
7
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]8/ {
9 wdt-reboot {
10 compatible = "wdt-reboot";
11 wdt = <&wdog3>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]12 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]13 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]14 };
15
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]16 firmware {
17 optee {
18 compatible = "linaro,optee-tz";
19 method = "smc";
20 };
21 };
22};
23
24&{/soc@0} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-all;
26 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]27};
28
29&aips1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
31 bootph-all;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]32};
33
34&aips2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]36 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]37};
38
39&aips3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]40 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]41 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]42};
43
44&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]46 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]47};
48
49&reg_usdhc2_vmmc {
50 u-boot,off-on-delay-us = <20000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]52 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]53};
54
55&pinctrl_reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]56 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]57};
58
59&pinctrl_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]60 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]61 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]62};
63
64&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]66 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]67};
68
69&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]71 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]72};
73
74&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]76 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]77};
78
79&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]81 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]82};
83
84&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]86 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]87};
88
89&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]90 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]91 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]92};
93
94&lpuart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]96 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]97};
98
99&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]100 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]101 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]102};
103
104&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]105 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]106 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]107 fsl,signal-voltage-switch-extra-delay-ms = <8>;
108};
109
110&lpi2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]111 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]112 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]113};
114
115&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]116 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]117 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]118};
119
120&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]121 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]122 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]123};
124
125&pinctrl_lpi2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]126 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]127 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]128};
129
130&fec {
131 phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
132 phy-reset-duration = <15>;
133 phy-reset-post-delay = <100>;
134};
135
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]136&ethphy1 {
137 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
138 reset-assert-us = <15000>;
139 reset-deassert-us = <100000>;
140};
141
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]142&s4muap {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]143 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]144 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]145 status = "okay";
146};
Sébastien Szymanski506d2062023-07-25 10:08:56 +0200[diff] [blame]147
148&clk {
149 bootph-all;
150 bootph-pre-ram;
151 /delete-property/ assigned-clocks;
152 /delete-property/ assigned-clock-rates;
153 /delete-property/ assigned-clock-parents;
154};
155
156&osc_32k {
157 bootph-all;
158 bootph-pre-ram;
159};
160
161&osc_24m {
162 bootph-all;
163 bootph-pre-ram;
164};
165
166&clk_ext1 {
167 bootph-all;
168 bootph-pre-ram;
169};