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git01.mediatek.com / filogic / uboot / 9b832adf58cac47b926991379c78af1d07bc3fed / . / arch / arm / dts / imx93-11x11-evk-u-boot.dtsi
blob: 4ecb53ed8be1a30ab110d33ba13289bc3c06cd61 [file] [log] [blame]
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2022 NXP
4 */
5
6/ {
7 wdt-reboot {
8 compatible = "wdt-reboot";
9 wdt = <&wdog3>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]10 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]11 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]12 };
13
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]14 firmware {
15 optee {
16 compatible = "linaro,optee-tz";
17 method = "smc";
18 };
19 };
20};
21
22&{/soc@0} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]23 bootph-all;
24 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]25};
26
27&aips1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]28 bootph-pre-ram;
29 bootph-all;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]30};
31
32&aips2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]34 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]35};
36
37&aips3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]39 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]40};
41
42&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]44 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]45};
46
47&reg_usdhc2_vmmc {
48 u-boot,off-on-delay-us = <20000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]50 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]51};
52
53&pinctrl_reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]55};
56
57&pinctrl_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]59 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]60};
61
62&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]64 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]65};
66
67&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]68 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]69 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]70};
71
72&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]74 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]75};
76
77&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]79 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]80};
81
82&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]84 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]85};
86
87&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]89 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]90};
91
92&lpuart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]93 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]94 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]95};
96
97&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]98 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]99 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]100};
101
102&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]104 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]105 fsl,signal-voltage-switch-extra-delay-ms = <8>;
106};
107
108&lpi2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]110 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]111};
112
113&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]114 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]115 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]116};
117
118&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]119 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]120 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]121};
122
123&pinctrl_lpi2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]124 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]125 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]126};
127
128&fec {
129 phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
130 phy-reset-duration = <15>;
131 phy-reset-post-delay = <100>;
132};
133
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]134&ethphy1 {
135 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
136 reset-assert-us = <15000>;
137 reset-deassert-us = <100000>;
138};
139
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]140&s4muap {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]141 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]142 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]143 status = "okay";
144};
Sébastien Szymanski506d2062023-07-25 10:08:56 +0200[diff] [blame]145
146&clk {
147 bootph-all;
148 bootph-pre-ram;
149 /delete-property/ assigned-clocks;
150 /delete-property/ assigned-clock-rates;
151 /delete-property/ assigned-clock-parents;
152};
153
154&osc_32k {
155 bootph-all;
156 bootph-pre-ram;
157};
158
159&osc_24m {
160 bootph-all;
161 bootph-pre-ram;
162};
163
164&clk_ext1 {
165 bootph-all;
166 bootph-pre-ram;
167};