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git01.mediatek.com / filogic / uboot / 0e548f0823938b3ddc5e69c6a4506121688f5235 / . / arch / arm / mach-exynos / clock_init.h
blob: 8664f10df4484a2b4fcc921cb2f9f84a3d134ee8 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]2/*
3 * Clock initialization routines
4 *
5 * Copyright (c) 2011 The Chromium OS Authors.
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]6 */
7
8#ifndef __EXYNOS_CLOCK_INIT_H
9#define __EXYNOS_CLOCK_INIT_H
10
11enum {
Rajeshwari Birjeac892d02013-12-26 09:44:21 +0530[diff] [blame]12#ifdef CONFIG_EXYNOS5420
13 MEM_TIMINGS_MSR_COUNT = 5,
14#else
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]15 MEM_TIMINGS_MSR_COUNT = 4,
Rajeshwari Birjeac892d02013-12-26 09:44:21 +0530[diff] [blame]16#endif
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]17};
18
19/* These are the ratio's for configuring ARM clock */
20struct arm_clk_ratios {
21 unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */
22
23 unsigned apll_mdiv;
24 unsigned apll_pdiv;
25 unsigned apll_sdiv;
26
27 unsigned arm2_ratio;
28 unsigned apll_ratio;
29 unsigned pclk_dbg_ratio;
30 unsigned atb_ratio;
31 unsigned periph_ratio;
32 unsigned acp_ratio;
33 unsigned cpud_ratio;
34 unsigned arm_ratio;
35};
36
37/* These are the memory timings for a particular memory type and speed */
38struct mem_timings {
39 enum mem_manuf mem_manuf; /* Memory manufacturer */
40 enum ddr_mode mem_type; /* Memory type */
41 unsigned frequency_mhz; /* Frequency of memory in MHz */
42
43 /* Here follow the timing parameters for the selected memory */
44 unsigned apll_mdiv;
45 unsigned apll_pdiv;
46 unsigned apll_sdiv;
47 unsigned mpll_mdiv;
48 unsigned mpll_pdiv;
49 unsigned mpll_sdiv;
50 unsigned cpll_mdiv;
51 unsigned cpll_pdiv;
52 unsigned cpll_sdiv;
53 unsigned gpll_mdiv;
54 unsigned gpll_pdiv;
55 unsigned gpll_sdiv;
56 unsigned epll_mdiv;
57 unsigned epll_pdiv;
58 unsigned epll_sdiv;
59 unsigned vpll_mdiv;
60 unsigned vpll_pdiv;
61 unsigned vpll_sdiv;
62 unsigned bpll_mdiv;
63 unsigned bpll_pdiv;
64 unsigned bpll_sdiv;
Rajeshwari Birjeac892d02013-12-26 09:44:21 +0530[diff] [blame]65 unsigned kpll_mdiv;
66 unsigned kpll_pdiv;
67 unsigned kpll_sdiv;
68 unsigned dpll_mdiv;
69 unsigned dpll_pdiv;
70 unsigned dpll_sdiv;
71 unsigned ipll_mdiv;
72 unsigned ipll_pdiv;
73 unsigned ipll_sdiv;
74 unsigned spll_mdiv;
75 unsigned spll_pdiv;
76 unsigned spll_sdiv;
Ajay Kumar218eaf32014-09-05 16:53:31 +0530[diff] [blame]77 unsigned rpll_mdiv;
78 unsigned rpll_pdiv;
79 unsigned rpll_sdiv;
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]80 unsigned pclk_cdrex_ratio;
81 unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
82
83 unsigned timing_ref;
84 unsigned timing_row;
85 unsigned timing_data;
86 unsigned timing_power;
87
88 /* DQS, DQ, DEBUG offsets */
89 unsigned phy0_dqs;
90 unsigned phy1_dqs;
91 unsigned phy0_dq;
92 unsigned phy1_dq;
93 unsigned phy0_tFS;
94 unsigned phy1_tFS;
95 unsigned phy0_pulld_dqs;
96 unsigned phy1_pulld_dqs;
97
98 unsigned lpddr3_ctrl_phy_reset;
99 unsigned ctrl_start_point;
100 unsigned ctrl_inc;
101 unsigned ctrl_start;
102 unsigned ctrl_dll_on;
103 unsigned ctrl_ref;
104
105 unsigned ctrl_force;
106 unsigned ctrl_rdlat;
107 unsigned ctrl_bstlen;
108
109 unsigned fp_resync;
110 unsigned iv_size;
111 unsigned dfi_init_start;
112 unsigned aref_en;
113
114 unsigned rd_fetch;
115
116 unsigned zq_mode_dds;
117 unsigned zq_mode_term;
118 unsigned zq_mode_noterm; /* 1 to allow termination disable */
119
120 unsigned memcontrol;
121 unsigned memconfig;
122
123 unsigned membaseconfig0;
124 unsigned membaseconfig1;
125 unsigned prechconfig_tp_cnt;
126 unsigned dpwrdn_cyc;
127 unsigned dsref_cyc;
128 unsigned concontrol;
129 /* Channel and Chip Selection */
130 uint8_t dmc_channels; /* number of memory channels */
131 uint8_t chips_per_channel; /* number of chips per channel */
132 uint8_t chips_to_configure; /* number of chips to configure */
133 uint8_t send_zq_init; /* 1 to send this command */
134 unsigned impedance; /* drive strength impedeance */
135 uint8_t gate_leveling_enable; /* check gate leveling is enabled */
Rajeshwari Birjeac892d02013-12-26 09:44:21 +0530[diff] [blame]136 uint8_t read_leveling_enable; /* check h/w read leveling is enabled */
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]137};
138
139/**
140 * Get the correct memory timings for our selected memory type and speed.
141 *
142 * This function can be called from SPL or the main U-Boot.
143 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100[diff] [blame]144 * Return: pointer to the memory timings that we should use
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]145 */
146struct mem_timings *clock_get_mem_timings(void);
147
148/*
149 * Initialize clock for the device
150 */
151void system_clock_init(void);
Amare33add82013-04-27 11:42:59 +0530[diff] [blame]152
153/*
154 * Set clock divisor value for booting from EMMC.
155 */
156void emmc_boot_clk_div_set(void);
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]157#endif