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git01.mediatek.com / filogic / uboot / ac892d06a8b86699ea0752979f89a7e3f3097e25 / . / arch / arm / cpu / armv7 / exynos / clock_init.h
blob: a875d0b48f6d651313ffaef8a937bff45f9bd4cd [file] [log] [blame]
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]1/*
2 * Clock initialization routines
3 *
4 * Copyright (c) 2011 The Chromium OS Authors.
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]6 * SPDX-License-Identifier: GPL-2.0+
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]7 */
8
9#ifndef __EXYNOS_CLOCK_INIT_H
10#define __EXYNOS_CLOCK_INIT_H
11
12enum {
Rajeshwari Birjeac892d02013-12-26 09:44:21 +0530[diff] [blame^]13#ifdef CONFIG_EXYNOS5420
14 MEM_TIMINGS_MSR_COUNT = 5,
15#else
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]16 MEM_TIMINGS_MSR_COUNT = 4,
Rajeshwari Birjeac892d02013-12-26 09:44:21 +0530[diff] [blame^]17#endif
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]18};
19
20/* These are the ratio's for configuring ARM clock */
21struct arm_clk_ratios {
22 unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */
23
24 unsigned apll_mdiv;
25 unsigned apll_pdiv;
26 unsigned apll_sdiv;
27
28 unsigned arm2_ratio;
29 unsigned apll_ratio;
30 unsigned pclk_dbg_ratio;
31 unsigned atb_ratio;
32 unsigned periph_ratio;
33 unsigned acp_ratio;
34 unsigned cpud_ratio;
35 unsigned arm_ratio;
36};
37
38/* These are the memory timings for a particular memory type and speed */
39struct mem_timings {
40 enum mem_manuf mem_manuf; /* Memory manufacturer */
41 enum ddr_mode mem_type; /* Memory type */
42 unsigned frequency_mhz; /* Frequency of memory in MHz */
43
44 /* Here follow the timing parameters for the selected memory */
45 unsigned apll_mdiv;
46 unsigned apll_pdiv;
47 unsigned apll_sdiv;
48 unsigned mpll_mdiv;
49 unsigned mpll_pdiv;
50 unsigned mpll_sdiv;
51 unsigned cpll_mdiv;
52 unsigned cpll_pdiv;
53 unsigned cpll_sdiv;
54 unsigned gpll_mdiv;
55 unsigned gpll_pdiv;
56 unsigned gpll_sdiv;
57 unsigned epll_mdiv;
58 unsigned epll_pdiv;
59 unsigned epll_sdiv;
60 unsigned vpll_mdiv;
61 unsigned vpll_pdiv;
62 unsigned vpll_sdiv;
63 unsigned bpll_mdiv;
64 unsigned bpll_pdiv;
65 unsigned bpll_sdiv;
Rajeshwari Birjeac892d02013-12-26 09:44:21 +0530[diff] [blame^]66 unsigned kpll_mdiv;
67 unsigned kpll_pdiv;
68 unsigned kpll_sdiv;
69 unsigned dpll_mdiv;
70 unsigned dpll_pdiv;
71 unsigned dpll_sdiv;
72 unsigned ipll_mdiv;
73 unsigned ipll_pdiv;
74 unsigned ipll_sdiv;
75 unsigned spll_mdiv;
76 unsigned spll_pdiv;
77 unsigned spll_sdiv;
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]78 unsigned pclk_cdrex_ratio;
79 unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
80
81 unsigned timing_ref;
82 unsigned timing_row;
83 unsigned timing_data;
84 unsigned timing_power;
85
86 /* DQS, DQ, DEBUG offsets */
87 unsigned phy0_dqs;
88 unsigned phy1_dqs;
89 unsigned phy0_dq;
90 unsigned phy1_dq;
91 unsigned phy0_tFS;
92 unsigned phy1_tFS;
93 unsigned phy0_pulld_dqs;
94 unsigned phy1_pulld_dqs;
95
96 unsigned lpddr3_ctrl_phy_reset;
97 unsigned ctrl_start_point;
98 unsigned ctrl_inc;
99 unsigned ctrl_start;
100 unsigned ctrl_dll_on;
101 unsigned ctrl_ref;
102
103 unsigned ctrl_force;
104 unsigned ctrl_rdlat;
105 unsigned ctrl_bstlen;
106
107 unsigned fp_resync;
108 unsigned iv_size;
109 unsigned dfi_init_start;
110 unsigned aref_en;
111
112 unsigned rd_fetch;
113
114 unsigned zq_mode_dds;
115 unsigned zq_mode_term;
116 unsigned zq_mode_noterm; /* 1 to allow termination disable */
117
118 unsigned memcontrol;
119 unsigned memconfig;
120
121 unsigned membaseconfig0;
122 unsigned membaseconfig1;
123 unsigned prechconfig_tp_cnt;
124 unsigned dpwrdn_cyc;
125 unsigned dsref_cyc;
126 unsigned concontrol;
127 /* Channel and Chip Selection */
128 uint8_t dmc_channels; /* number of memory channels */
129 uint8_t chips_per_channel; /* number of chips per channel */
130 uint8_t chips_to_configure; /* number of chips to configure */
131 uint8_t send_zq_init; /* 1 to send this command */
132 unsigned impedance; /* drive strength impedeance */
133 uint8_t gate_leveling_enable; /* check gate leveling is enabled */
Rajeshwari Birjeac892d02013-12-26 09:44:21 +0530[diff] [blame^]134 uint8_t read_leveling_enable; /* check h/w read leveling is enabled */
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]135};
136
137/**
138 * Get the correct memory timings for our selected memory type and speed.
139 *
140 * This function can be called from SPL or the main U-Boot.
141 *
142 * @return pointer to the memory timings that we should use
143 */
144struct mem_timings *clock_get_mem_timings(void);
145
146/*
147 * Initialize clock for the device
148 */
149void system_clock_init(void);
Amare33add82013-04-27 11:42:59 +0530[diff] [blame]150
151/*
152 * Set clock divisor value for booting from EMMC.
153 */
154void emmc_boot_clk_div_set(void);
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]155#endif