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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass509805b2015-01-27 22:13:39 -07002/*
3 * Copyright (C) 2015, Google, Inc
4 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
Simon Glass509805b2015-01-27 22:13:39 -07005 */
6
Simon Glass828b7252017-07-30 19:24:01 -07007#include <dm.h>
Simon Glass509805b2015-01-27 22:13:39 -07008#include <errno.h>
Simon Glass5eb66392020-07-07 21:32:12 -06009#include <log.h>
Simon Glass509805b2015-01-27 22:13:39 -070010#include <malloc.h>
Simon Glass828b7252017-07-30 19:24:01 -070011#include <mapmem.h>
Simon Glass74aaa3f2021-01-13 20:29:54 -070012#include <mmc.h>
Simon Glass509805b2015-01-27 22:13:39 -070013#include <sdhci.h>
Simon Glass5eb66392020-07-07 21:32:12 -060014#include <acpi/acpigen.h>
15#include <acpi/acpi_device.h>
16#include <acpi/acpi_dp.h>
17#include <asm-generic/gpio.h>
18#include <dm/acpi.h>
Simon Glass509805b2015-01-27 22:13:39 -070019
Simon Glass5c9c49e2021-01-13 20:29:52 -070020/* Type of MMC device */
21enum {
22 TYPE_SD,
23 TYPE_EMMC,
24};
25
Simon Glass828b7252017-07-30 19:24:01 -070026struct pci_mmc_plat {
27 struct mmc_config cfg;
28 struct mmc mmc;
29};
30
31struct pci_mmc_priv {
32 struct sdhci_host host;
33 void *base;
Simon Glass5eb66392020-07-07 21:32:12 -060034 struct gpio_desc cd_gpio;
Simon Glass828b7252017-07-30 19:24:01 -070035};
36
37static int pci_mmc_probe(struct udevice *dev)
Simon Glass509805b2015-01-27 22:13:39 -070038{
Simon Glass828b7252017-07-30 19:24:01 -070039 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
Simon Glassfa20e932020-12-03 16:55:20 -070040 struct pci_mmc_plat *plat = dev_get_plat(dev);
Simon Glass828b7252017-07-30 19:24:01 -070041 struct pci_mmc_priv *priv = dev_get_priv(dev);
42 struct sdhci_host *host = &priv->host;
Simon Glass74aaa3f2021-01-13 20:29:54 -070043 struct blk_desc *desc;
Simon Glass509805b2015-01-27 22:13:39 -070044 int ret;
Simon Glass509805b2015-01-27 22:13:39 -070045
Simon Glass74aaa3f2021-01-13 20:29:54 -070046 ret = mmc_of_parse(dev, &plat->cfg);
47 if (ret)
48 return ret;
49 desc = mmc_get_blk_desc(&plat->mmc);
50 desc->removable = !(plat->cfg.host_caps & MMC_CAP_NONREMOVABLE);
51
Bin Mengc8b284e2023-10-11 19:00:52 +080052 host->ioaddr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
53 PCI_REGION_TYPE, PCI_REGION_MEM);
Simon Glass828b7252017-07-30 19:24:01 -070054 host->name = dev->name;
Simon Glass2001f4a2021-03-15 18:00:08 +130055 host->cd_gpio = priv->cd_gpio;
Peng Fan798f2e82019-08-06 02:47:56 +000056 host->mmc = &plat->mmc;
57 host->mmc->dev = dev;
Simon Glass828b7252017-07-30 19:24:01 -070058 ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
59 if (ret)
60 return ret;
Simon Glass828b7252017-07-30 19:24:01 -070061 host->mmc->priv = &priv->host;
Simon Glass828b7252017-07-30 19:24:01 -070062 upriv->mmc = host->mmc;
Simon Glass509805b2015-01-27 22:13:39 -070063
Simon Glass828b7252017-07-30 19:24:01 -070064 return sdhci_probe(dev);
65}
Simon Glass509805b2015-01-27 22:13:39 -070066
Simon Glassaad29ae2020-12-03 16:55:21 -070067static int pci_mmc_of_to_plat(struct udevice *dev)
Simon Glass5eb66392020-07-07 21:32:12 -060068{
Harm Berntsen6ca79a22020-11-06 12:20:44 +000069 if (CONFIG_IS_ENABLED(DM_GPIO)) {
70 struct pci_mmc_priv *priv = dev_get_priv(dev);
Simon Glass2001f4a2021-03-15 18:00:08 +130071 int ret;
Simon Glass5eb66392020-07-07 21:32:12 -060072
Simon Glass2001f4a2021-03-15 18:00:08 +130073 ret = gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
74 GPIOD_IS_IN);
75 log_debug("cd-gpio %s done, ret=%d\n", dev->name, ret);
Harm Berntsen6ca79a22020-11-06 12:20:44 +000076 }
Simon Glass5eb66392020-07-07 21:32:12 -060077
78 return 0;
79}
80
Simon Glass828b7252017-07-30 19:24:01 -070081static int pci_mmc_bind(struct udevice *dev)
82{
Simon Glassfa20e932020-12-03 16:55:20 -070083 struct pci_mmc_plat *plat = dev_get_plat(dev);
Simon Glass509805b2015-01-27 22:13:39 -070084
Simon Glass828b7252017-07-30 19:24:01 -070085 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
Simon Glass509805b2015-01-27 22:13:39 -070086}
Simon Glass828b7252017-07-30 19:24:01 -070087
Heinrich Schuchardt93a7aff2022-06-12 12:53:48 +000088__maybe_unused
Simon Glass5eb66392020-07-07 21:32:12 -060089static int pci_mmc_acpi_fill_ssdt(const struct udevice *dev,
90 struct acpi_ctx *ctx)
91{
92 struct pci_mmc_priv *priv = dev_get_priv(dev);
93 char path[ACPI_PATH_MAX];
94 struct acpi_gpio gpio;
95 struct acpi_dp *dp;
96 int ret;
97
Simon Glassf1d50f72020-12-19 10:40:13 -070098 if (!dev_has_ofnode(dev))
Simon Glass5eb66392020-07-07 21:32:12 -060099 return 0;
Simon Glass5c9c49e2021-01-13 20:29:52 -0700100 if (dev_get_driver_data(dev) == TYPE_EMMC)
101 return 0;
Simon Glass5eb66392020-07-07 21:32:12 -0600102
103 ret = gpio_get_acpi(&priv->cd_gpio, &gpio);
104 if (ret)
105 return log_msg_ret("gpio", ret);
106 gpio.type = ACPI_GPIO_TYPE_INTERRUPT;
107 gpio.pull = ACPI_GPIO_PULL_NONE;
108 gpio.irq.mode = ACPI_IRQ_EDGE_TRIGGERED;
109 gpio.irq.polarity = ACPI_IRQ_ACTIVE_BOTH;
110 gpio.irq.shared = ACPI_IRQ_SHARED;
111 gpio.irq.wake = ACPI_IRQ_WAKE;
112 gpio.interrupt_debounce_timeout = 10000; /* 100ms */
113
114 /* Use device path as the Scope for the SSDT */
115 ret = acpi_device_path(dev, path, sizeof(path));
116 if (ret)
117 return log_msg_ret("path", ret);
118 acpigen_write_scope(ctx, path);
119 acpigen_write_name(ctx, "_CRS");
120
121 /* Write GpioInt() as default (if set) or custom from devicetree */
122 acpigen_write_resourcetemplate_header(ctx);
123 acpi_device_write_gpio(ctx, &gpio);
124 acpigen_write_resourcetemplate_footer(ctx);
125
126 /* Bind the cd-gpio name to the GpioInt() resource */
127 dp = acpi_dp_new_table("_DSD");
128 if (!dp)
129 return -ENOMEM;
130 acpi_dp_add_gpio(dp, "cd-gpio", path, 0, 0, 1);
131 ret = acpi_dp_write(ctx, dp);
132 if (ret)
133 return log_msg_ret("cd", ret);
134
135 acpigen_pop_len(ctx);
136
137 return 0;
138}
139
140struct acpi_ops pci_mmc_acpi_ops = {
Heinrich Schuchardt93a7aff2022-06-12 12:53:48 +0000141#ifdef CONFIG_ACPIGEN
Simon Glass5eb66392020-07-07 21:32:12 -0600142 .fill_ssdt = pci_mmc_acpi_fill_ssdt,
Heinrich Schuchardt93a7aff2022-06-12 12:53:48 +0000143#endif
Simon Glass5eb66392020-07-07 21:32:12 -0600144};
145
146static const struct udevice_id pci_mmc_match[] = {
Simon Glass5c9c49e2021-01-13 20:29:52 -0700147 { .compatible = "intel,apl-sd", .data = TYPE_SD },
148 { .compatible = "intel,apl-emmc", .data = TYPE_EMMC },
Simon Glass5eb66392020-07-07 21:32:12 -0600149 { }
150};
151
Simon Glass828b7252017-07-30 19:24:01 -0700152U_BOOT_DRIVER(pci_mmc) = {
153 .name = "pci_mmc",
154 .id = UCLASS_MMC,
Simon Glass5eb66392020-07-07 21:32:12 -0600155 .of_match = pci_mmc_match,
Simon Glass828b7252017-07-30 19:24:01 -0700156 .bind = pci_mmc_bind,
Simon Glassaad29ae2020-12-03 16:55:21 -0700157 .of_to_plat = pci_mmc_of_to_plat,
Simon Glass828b7252017-07-30 19:24:01 -0700158 .probe = pci_mmc_probe,
159 .ops = &sdhci_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700160 .priv_auto = sizeof(struct pci_mmc_priv),
Simon Glass71fa5b42020-12-03 16:55:18 -0700161 .plat_auto = sizeof(struct pci_mmc_plat),
Simon Glass5eb66392020-07-07 21:32:12 -0600162 ACPI_OPS_PTR(&pci_mmc_acpi_ops)
Simon Glass828b7252017-07-30 19:24:01 -0700163};
164
165static struct pci_device_id mmc_supported[] = {
Bin Meng77520f82017-08-09 00:21:00 -0700166 { PCI_DEVICE_CLASS(PCI_CLASS_SYSTEM_SDHCI << 8, 0xffff00) },
Simon Glass828b7252017-07-30 19:24:01 -0700167 {},
168};
169
170U_BOOT_PCI_DEVICE(pci_mmc, mmc_supported);