| Shaohui Xie | c9ed7bd | 2013-09-22 09:56:02 +0800 | [diff] [blame] | 1 | #PBI commands |
| 2 | #Initialize CPC1 |
| 3 | 09010000 00200400 |
| 4 | 09138000 00000000 |
| 5 | 091380c0 00000100 |
| 6 | #Configure CPC1 as 512KB SRAM |
| 7 | 09010100 00000000 |
| 8 | 09010104 fff80009 |
| 9 | 09010f00 08000000 |
| 10 | 09010000 80000000 |
| 11 | #Configure LAW for CPC1 |
| 12 | 09000d00 00000000 |
| 13 | 09000d04 fff80000 |
| 14 | 09000d08 81000012 |
| 15 | #Configure alternate space |
| 16 | 09000010 00000000 |
| 17 | 09000014 ff000000 |
| 18 | 09000018 81000000 |
| 19 | #Configure SPI controller |
| 20 | 09110000 80000403 |
| 21 | 09110020 2d170008 |
| 22 | 09110024 00100008 |
| 23 | 09110028 00100008 |
| 24 | 0911002c 00100008 |
| Prabhakar Kushwaha | 04bfe20 | 2014-03-08 16:45:04 +0530 | [diff] [blame] | 25 | #slowing down the MDC clock to make it <= 2.5 MHZ |
| 26 | 094fc030 00008148 |
| 27 | 094fd030 00008148 |
| Shaohui Xie | c9ed7bd | 2013-09-22 09:56:02 +0800 | [diff] [blame] | 28 | #Flush PBL data |
| 29 | 09138000 00000000 |
| 30 | 091380c0 00000000 |