| commit | 04bfe207ee62408d0f5f810329aa1c8cbb9ab59b | [log] [tgz] |
|---|---|---|
| author | Prabhakar Kushwaha <prabhakar@freescale.com> | Sat Mar 08 16:45:04 2014 +0530 |
| committer | York Sun <yorksun@freescale.com> | Tue Apr 22 17:58:47 2014 -0700 |
| tree | 089b64c9c4d6bf24e0e030bdf5668b330658395b | |
| parent | 3c49424779968776bdfda290f54456d8f92c323b [diff] |
board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher than 2.5 MHZ. It violates the IEEE specs. So Slow MDC clock to comply IEEE specs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>