tree 089b64c9c4d6bf24e0e030bdf5668b330658395b
parent 3c49424779968776bdfda290f54456d8f92c323b
author Prabhakar Kushwaha <prabhakar@freescale.com> 1394277304 +0530
committer York Sun <yorksun@freescale.com> 1398214727 -0700

board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config

The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher
than 2.5 MHZ.  It violates the IEEE specs.

So Slow MDC clock to comply IEEE specs

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>