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Sergey Kubushyne8f39122007-08-10 20:26:18 +02001/*
2 * Intel LXT971/LXT972 PHY Driver for TI DaVinci
3 * (TMS320DM644x) based boards.
4 *
5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 *
7 * --------------------------------------------------------
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <net.h>
Hugo Villeneuve72c01d32008-06-18 12:10:31 -040030#include <miiphy.h>
Sergey Kubushyne8f39122007-08-10 20:26:18 +020031#include <lxt971a.h>
32#include <asm/arch/emac_defs.h>
Ilya Yanok5f732f72011-11-28 06:37:29 +000033#include "../../../../../drivers/net/davinci_emac.h"
Sergey Kubushyne8f39122007-08-10 20:26:18 +020034
35#ifdef CONFIG_DRIVER_TI_EMAC
36
37#ifdef CONFIG_CMD_NET
38
39int lxt972_is_phy_connected(int phy_addr)
40{
Hugo Villeneuve070911d2008-06-18 12:10:33 -040041 u_int16_t id1, id2;
Sergey Kubushyne8f39122007-08-10 20:26:18 +020042
Mike Frysingerd63ee712010-12-23 15:40:12 -050043 if (!davinci_eth_phy_read(phy_addr, MII_PHYSID1, &id1))
Sergey Kubushyne8f39122007-08-10 20:26:18 +020044 return(0);
Mike Frysingerd63ee712010-12-23 15:40:12 -050045 if (!davinci_eth_phy_read(phy_addr, MII_PHYSID2, &id2))
Sergey Kubushyne8f39122007-08-10 20:26:18 +020046 return(0);
47
48 if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0))
49 return(1);
50
51 return(0);
52}
53
54int lxt972_get_link_speed(int phy_addr)
55{
Hugo Villeneuve070911d2008-06-18 12:10:33 -040056 u_int16_t stat1, tmp;
57 volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
Sergey Kubushyne8f39122007-08-10 20:26:18 +020058
Sandeep Paulraj4b26f052008-08-31 00:39:46 +020059 if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1))
Sergey Kubushyne8f39122007-08-10 20:26:18 +020060 return(0);
61
62 if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link up? */
63 return(0);
64
Sandeep Paulraj4b26f052008-08-31 00:39:46 +020065 if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
Sergey Kubushyne8f39122007-08-10 20:26:18 +020066 return(0);
67
68 tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE;
69
Sandeep Paulraj4b26f052008-08-31 00:39:46 +020070 davinci_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp);
Sergey Kubushyne8f39122007-08-10 20:26:18 +020071 /* Read back */
Sandeep Paulraj4b26f052008-08-31 00:39:46 +020072 if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
Sergey Kubushyne8f39122007-08-10 20:26:18 +020073 return(0);
74
Sergey Kubushyne8f39122007-08-10 20:26:18 +020075 /* Speed doesn't matter, there is no setting for it in EMAC... */
Hugo Villeneuve070911d2008-06-18 12:10:33 -040076 if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
77 /* set DM644x EMAC for Full Duplex */
78 emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
79 EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
Sergey Kubushyne8f39122007-08-10 20:26:18 +020080 } else {
Hugo Villeneuve070911d2008-06-18 12:10:33 -040081 /*set DM644x EMAC for Half Duplex */
82 emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
Sergey Kubushyne8f39122007-08-10 20:26:18 +020083 }
84
Hugo Villeneuve070911d2008-06-18 12:10:33 -040085 return(1);
Sergey Kubushyne8f39122007-08-10 20:26:18 +020086}
87
88
89int lxt972_init_phy(int phy_addr)
90{
Hugo Villeneuve070911d2008-06-18 12:10:33 -040091 int ret = 1;
Sergey Kubushyne8f39122007-08-10 20:26:18 +020092
93 if (!lxt972_get_link_speed(phy_addr)) {
94 /* Try another time */
95 ret = lxt972_get_link_speed(phy_addr);
96 }
97
98 /* Disable PHY Interrupts */
Sandeep Paulraj4b26f052008-08-31 00:39:46 +020099 davinci_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0);
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200100
101 return(ret);
102}
103
104
105int lxt972_auto_negotiate(int phy_addr)
106{
Hugo Villeneuve070911d2008-06-18 12:10:33 -0400107 u_int16_t tmp;
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200108
Mike Frysingerd63ee712010-12-23 15:40:12 -0500109 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200110 return(0);
111
112 /* Restart Auto_negotiation */
Mike Frysingerd63ee712010-12-23 15:40:12 -0500113 tmp |= BMCR_ANRESTART;
114 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200115
116 /*check AutoNegotiate complete */
117 udelay (10000);
Mike Frysingerd63ee712010-12-23 15:40:12 -0500118 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200119 return(0);
120
Mike Frysingerd63ee712010-12-23 15:40:12 -0500121 if (!(tmp & BMSR_ANEGCOMPLETE))
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200122 return(0);
123
124 return (lxt972_get_link_speed(phy_addr));
125}
126
127#endif /* CONFIG_CMD_NET */
128
129#endif /* CONFIG_DRIVER_ETHER */