Ruchika Gupta | ac1b269 | 2014-10-15 11:35:30 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008-2014 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef __JR_H |
| 9 | #define __JR_H |
| 10 | |
| 11 | #include <linux/compiler.h> |
| 12 | |
| 13 | #define JR_SIZE 4 |
| 14 | /* Timeout currently defined as 90 sec */ |
| 15 | #define CONFIG_SEC_DEQ_TIMEOUT 90000000U |
| 16 | |
| 17 | #define DEFAULT_JR_ID 0 |
| 18 | #define DEFAULT_JR_LIODN 0 |
| 19 | #define DEFAULT_IRQ 0 /* Interrupts not to be configured */ |
| 20 | |
| 21 | #define MCFGR_SWRST ((uint32_t)(1)<<31) /* Software Reset */ |
| 22 | #define MCFGR_DMA_RST ((uint32_t)(1)<<28) /* DMA Reset */ |
| 23 | #define MCFGR_PS_SHIFT 16 |
horia.geanta@freescale.com | 66e26aa | 2015-07-08 17:24:57 +0300 | [diff] [blame] | 24 | #define MCFGR_AWCACHE_SHIFT 8 |
| 25 | #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) |
Saksham Jain | 0c19cea | 2016-03-23 16:24:42 +0530 | [diff] [blame^] | 26 | #define MCFGR_ARCACHE_SHIFT 12 |
| 27 | #define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) |
| 28 | |
Ruchika Gupta | ac1b269 | 2014-10-15 11:35:30 +0530 | [diff] [blame] | 29 | #define JR_INTMASK 0x00000001 |
| 30 | #define JRCR_RESET 0x01 |
| 31 | #define JRINT_ERR_HALT_INPROGRESS 0x4 |
| 32 | #define JRINT_ERR_HALT_MASK 0xc |
| 33 | #define JRNSLIODN_SHIFT 16 |
| 34 | #define JRNSLIODN_MASK 0x0fff0000 |
| 35 | #define JRSLIODN_SHIFT 0 |
| 36 | #define JRSLIODN_MASK 0x00000fff |
| 37 | |
| 38 | #define JQ_DEQ_ERR -1 |
| 39 | #define JQ_DEQ_TO_ERR -2 |
| 40 | #define JQ_ENQ_ERR -3 |
| 41 | |
| 42 | struct op_ring { |
Aneesh Bansal | 4342182 | 2015-10-29 22:58:03 +0530 | [diff] [blame] | 43 | phys_addr_t desc; |
Ruchika Gupta | ac1b269 | 2014-10-15 11:35:30 +0530 | [diff] [blame] | 44 | uint32_t status; |
| 45 | } __packed; |
| 46 | |
| 47 | struct jr_info { |
Aneesh Bansal | 4342182 | 2015-10-29 22:58:03 +0530 | [diff] [blame] | 48 | void (*callback)(uint32_t status, void *arg); |
| 49 | phys_addr_t desc_phys_addr; |
Ruchika Gupta | ac1b269 | 2014-10-15 11:35:30 +0530 | [diff] [blame] | 50 | uint32_t desc_len; |
| 51 | uint32_t op_done; |
| 52 | void *arg; |
| 53 | }; |
| 54 | |
| 55 | struct jobring { |
| 56 | int jq_id; |
| 57 | int irq; |
| 58 | int liodn; |
| 59 | /* Head is the index where software would enq the descriptor in |
| 60 | * the i/p ring |
| 61 | */ |
| 62 | int head; |
| 63 | /* Tail index would be used by s/w ehile enqueuing to determine if |
| 64 | * there is any space left in the s/w maintained i/p rings |
| 65 | */ |
| 66 | /* Also in case of deq tail will be incremented only in case of |
| 67 | * in-order job completion |
| 68 | */ |
| 69 | int tail; |
| 70 | /* Read index of the output ring. It may not match with tail in case |
| 71 | * of out of order completetion |
| 72 | */ |
| 73 | int read_idx; |
| 74 | /* Write index to input ring. Would be always equal to head */ |
| 75 | int write_idx; |
| 76 | /* Size of the rings. */ |
| 77 | int size; |
Ruchika Gupta | d218033 | 2016-01-22 16:12:55 +0530 | [diff] [blame] | 78 | /* Op ring size aligned to cache line size */ |
| 79 | int op_size; |
Ruchika Gupta | ac1b269 | 2014-10-15 11:35:30 +0530 | [diff] [blame] | 80 | /* The ip and output rings have to be accessed by SEC. So the |
| 81 | * pointers will ahve to point to the housekeeping region provided |
| 82 | * by SEC |
| 83 | */ |
| 84 | /*Circular Ring of i/p descriptors */ |
| 85 | dma_addr_t *input_ring; |
| 86 | /* Circular Ring of o/p descriptors */ |
| 87 | /* Circula Ring containing info regarding descriptors in i/p |
| 88 | * and o/p ring |
| 89 | */ |
| 90 | /* This ring can be on the stack */ |
| 91 | struct jr_info info[JR_SIZE]; |
| 92 | struct op_ring *output_ring; |
| 93 | }; |
| 94 | |
| 95 | struct result { |
| 96 | int done; |
| 97 | uint32_t status; |
| 98 | }; |
| 99 | |
| 100 | void caam_jr_strstatus(u32 status); |
| 101 | int run_descriptor_jr(uint32_t *desc); |
| 102 | |
| 103 | #endif |