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Ruchika Guptaac1b2692014-10-15 11:35:30 +05301/*
2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 *
6 */
7
8#ifndef __JR_H
9#define __JR_H
10
11#include <linux/compiler.h>
12
13#define JR_SIZE 4
14/* Timeout currently defined as 90 sec */
15#define CONFIG_SEC_DEQ_TIMEOUT 90000000U
16
17#define DEFAULT_JR_ID 0
18#define DEFAULT_JR_LIODN 0
19#define DEFAULT_IRQ 0 /* Interrupts not to be configured */
20
21#define MCFGR_SWRST ((uint32_t)(1)<<31) /* Software Reset */
22#define MCFGR_DMA_RST ((uint32_t)(1)<<28) /* DMA Reset */
23#define MCFGR_PS_SHIFT 16
horia.geanta@freescale.com66e26aa2015-07-08 17:24:57 +030024#define MCFGR_AWCACHE_SHIFT 8
25#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)
Ruchika Guptaac1b2692014-10-15 11:35:30 +053026#define JR_INTMASK 0x00000001
27#define JRCR_RESET 0x01
28#define JRINT_ERR_HALT_INPROGRESS 0x4
29#define JRINT_ERR_HALT_MASK 0xc
30#define JRNSLIODN_SHIFT 16
31#define JRNSLIODN_MASK 0x0fff0000
32#define JRSLIODN_SHIFT 0
33#define JRSLIODN_MASK 0x00000fff
34
35#define JQ_DEQ_ERR -1
36#define JQ_DEQ_TO_ERR -2
37#define JQ_ENQ_ERR -3
38
39struct op_ring {
Aneesh Bansal43421822015-10-29 22:58:03 +053040 phys_addr_t desc;
Ruchika Guptaac1b2692014-10-15 11:35:30 +053041 uint32_t status;
42} __packed;
43
44struct jr_info {
Aneesh Bansal43421822015-10-29 22:58:03 +053045 void (*callback)(uint32_t status, void *arg);
46 phys_addr_t desc_phys_addr;
Ruchika Guptaac1b2692014-10-15 11:35:30 +053047 uint32_t desc_len;
48 uint32_t op_done;
49 void *arg;
50};
51
52struct jobring {
53 int jq_id;
54 int irq;
55 int liodn;
56 /* Head is the index where software would enq the descriptor in
57 * the i/p ring
58 */
59 int head;
60 /* Tail index would be used by s/w ehile enqueuing to determine if
61 * there is any space left in the s/w maintained i/p rings
62 */
63 /* Also in case of deq tail will be incremented only in case of
64 * in-order job completion
65 */
66 int tail;
67 /* Read index of the output ring. It may not match with tail in case
68 * of out of order completetion
69 */
70 int read_idx;
71 /* Write index to input ring. Would be always equal to head */
72 int write_idx;
73 /* Size of the rings. */
74 int size;
Ruchika Guptad2180332016-01-22 16:12:55 +053075 /* Op ring size aligned to cache line size */
76 int op_size;
Ruchika Guptaac1b2692014-10-15 11:35:30 +053077 /* The ip and output rings have to be accessed by SEC. So the
78 * pointers will ahve to point to the housekeeping region provided
79 * by SEC
80 */
81 /*Circular Ring of i/p descriptors */
82 dma_addr_t *input_ring;
83 /* Circular Ring of o/p descriptors */
84 /* Circula Ring containing info regarding descriptors in i/p
85 * and o/p ring
86 */
87 /* This ring can be on the stack */
88 struct jr_info info[JR_SIZE];
89 struct op_ring *output_ring;
90};
91
92struct result {
93 int done;
94 uint32_t status;
95};
96
97void caam_jr_strstatus(u32 status);
98int run_descriptor_jr(uint32_t *desc);
99
100#endif