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git01.mediatek.com / filogic / uboot / 0bc035f743d5c3058e10def7739dea89488749b1 / . / arch / powerpc / cpu / mpc83xx / elbc / Kconfig.elbc0
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Mario Six1faf95d2019-01-21 09:18:03 +0100[diff] [blame]1menuconfig ELBC_BR0_OR0
2 bool "ELBC BR0/OR0"
3
4if ELBC_BR0_OR0
5
6config BR0_OR0_NAME
7 string "Identifier"
8
9config BR0_OR0_BASE
10 hex "Port base"
11
12choice
13 prompt "Port size"
14
15config BR0_PORTSIZE_8BIT
16 bool "8-bit"
17
18config BR0_PORTSIZE_16BIT
19 depends on !BR0_MACHINE_FCM
20 bool "16-bit"
21
22
23config BR0_PORTSIZE_32BIT
24 depends on !BR0_MACHINE_FCM
25 depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
26 bool "32-bit"
27
28endchoice
29
30if BR0_MACHINE_FCM
31
32choice
33 prompt "Data Error Checking"
34
35config BR0_ERRORCHECKING_DISABLED
36 bool "Disabled"
37
38config BR0_ERRORCHECKING_ECC_CHECKING
39 bool "ECC checking / No ECC generation"
40
41config BR0_ERRORCHECKING_BOTH
42 bool "ECC checking and generation"
43
44endchoice
45
46endif
47
48config BR0_WRITE_PROTECT
49 bool "Write-protect"
50
51config BR0_MACHINE_UPM
52 bool
53
54choice
55 prompt "Machine select"
56
57config BR0_MACHINE_GPCM
58 bool "GPCM"
59
60config BR0_MACHINE_FCM
61 depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
62 bool "FCM"
63
64config BR0_MACHINE_SDRAM
65 depends on ARCH_MPC8349 || ARCH_MPC8360
66 bool "SDRAM"
67
68config BR0_MACHINE_UPMA
69 select BR0_MACHINE_UPM
70 bool "UPM (A)"
71
72config BR0_MACHINE_UPMB
73 select BR0_MACHINE_UPM
74 bool "UPM (B)"
75
76config BR0_MACHINE_UPMC
77 select BR0_MACHINE_UPM
78 bool "UPM (C)"
79
80endchoice
81
82if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
83
84choice
85 prompt "Atomic operations"
86
87config BR0_ATOMIC_NONE
88 bool "No atomic operations"
89
90config BR0_ATOMIC_RAWA
91 bool "Read-after-write-atomic"
92
93config BR0_ATOMIC_WARA
94 bool "Write-after-read-atomic"
95
96endchoice
97
98endif
99
100if BR0_MACHINE_GPCM || BR0_MACHINE_FCM || BR0_MACHINE_UPM || BR0_MACHINE_SDRAM
101
102choice
103 prompt "Address mask"
104
105config OR0_AM_32_KBYTES
106 depends on !BR0_MACHINE_SDRAM
107 bool "32 kb"
108
109config OR0_AM_64_KBYTES
110 bool "64 kb"
111
112config OR0_AM_128_KBYTES
113 bool "128 kb"
114
115config OR0_AM_256_KBYTES
116 bool "256 kb"
117
118config OR0_AM_512_KBYTES
119 bool "512 kb"
120
121config OR0_AM_1_MBYTES
122 bool "1 mb"
123
124config OR0_AM_2_MBYTES
125 bool "2 mb"
126
127config OR0_AM_4_MBYTES
128 bool "4 mb"
129
130config OR0_AM_8_MBYTES
131 bool "8 mb"
132
133config OR0_AM_16_MBYTES
134 bool "16 mb"
135
136config OR0_AM_32_MBYTES
137 bool "32 mb"
138
139config OR0_AM_64_MBYTES
140 bool "64 mb"
141
142# XXX: Some boards define 128MB AM with GPCM, even though it should not be
143# possible according to the manuals
144config OR0_AM_128_MBYTES
145 bool "128 mb"
146
147# XXX: Some boards define 256MB AM with GPCM, even though it should not be
148# possible according to the manuals
149config OR0_AM_256_MBYTES
150 bool "256 mb"
151
152config OR0_AM_512_MBYTES
153 depends on BR0_MACHINE_FCM
154 bool "512 mb"
155
156# XXX: Some boards define 1GB AM with GPCM, even though it should not be
157# possible according to the manuals
158config OR0_AM_1_GBYTES
159 bool "1 gb"
160
161config OR0_AM_2_GBYTES
162 depends on BR0_MACHINE_FCM
163 bool "2 gb"
164
165config OR0_AM_4_GBYTES
166 depends on BR0_MACHINE_FCM
167 bool "4 gb"
168
169endchoice
170
171config OR0_XAM_SET
172 bool "Set unused bytes after address mask"
173choice
174 prompt "Buffer control disable"
175
176config OR0_BCTLD_ASSERTED
177 bool "Asserted"
178
179config OR0_BCTLD_NOT_ASSERTED
180 bool "Not asserted"
181
182endchoice
183
184endif
185
186if BR0_MACHINE_GPCM || BR0_MACHINE_FCM
187
188choice
189 prompt "Cycle length in bus clocks"
190
191config OR0_SCY_0
192 bool "No wait states"
193
194config OR0_SCY_1
195 bool "1 wait state"
196
197config OR0_SCY_2
198 bool "2 wait states"
199
200config OR0_SCY_3
201 bool "3 wait states"
202
203config OR0_SCY_4
204 bool "4 wait states"
205
206config OR0_SCY_5
207 bool "5 wait states"
208
209config OR0_SCY_6
210 bool "6 wait states"
211
212config OR0_SCY_7
213 bool "7 wait states"
214
215config OR0_SCY_8
216 depends on BR0_MACHINE_GPCM
217 bool "8 wait states"
218
219config OR0_SCY_9
220 depends on BR0_MACHINE_GPCM
221 bool "9 wait states"
222
223config OR0_SCY_10
224 depends on BR0_MACHINE_GPCM
225 bool "10 wait states"
226
227config OR0_SCY_11
228 depends on BR0_MACHINE_GPCM
229 bool "11 wait states"
230
231config OR0_SCY_12
232 depends on BR0_MACHINE_GPCM
233 bool "12 wait states"
234
235config OR0_SCY_13
236 depends on BR0_MACHINE_GPCM
237 bool "13 wait states"
238
239config OR0_SCY_14
240 depends on BR0_MACHINE_GPCM
241 bool "14 wait states"
242
243config OR0_SCY_15
244 depends on BR0_MACHINE_GPCM
245 bool "15 wait states"
246
247endchoice
248
249endif # BR0_MACHINE_GPCM || BR0_MACHINE_FCM
250
251if BR0_MACHINE_GPCM
252
253choice
254 prompt "Chip select negotiation time"
255
256config OR0_CSNT_NORMAL
257 bool "Normal"
258
259config OR0_CSNT_EARLIER
260 bool "Earlier"
261
262endchoice
263
264choice
265 prompt "Address to chip-select setup"
266
267config OR0_ACS_SAME_TIME
268 bool "At the same time"
269
270config OR0_ACS_HALF_CYCLE_EARLIER
271 bool "Half of a bus clock cycle earlier"
272
273config OR0_ACS_QUARTER_CYCLE_EARLIER
274 bool "Half/Quarter of a bus clock cycle earlier"
275
276endchoice
277
278choice
279 prompt "Extra address to check-select setup"
280
281config OR0_XACS_NORMAL
282 bool "Normal"
283
284config OR0_XACS_EXTENDED
285 bool "Extended"
286
287endchoice
288
289choice
290 prompt "External address termination"
291
292config OR0_SETA_INTERNAL
293 bool "Access is terminated internally"
294
295config OR0_SETA_EXTERNAL
296 bool "Access is terminated externally"
297
298endchoice
299
300endif # BR0_MACHINE_GPCM
301
302if BR0_MACHINE_FCM
303
304choice
305 prompt "NAND Flash EEPROM page size"
306
307config OR0_PGS_SMALL
308 bool "Small page device"
309
310config OR0_PGS_LARGE
311 bool "Large page device"
312
313endchoice
314
315choice
316 prompt "Chip select to command time"
317
318config OR0_CSCT_1_CYCLE
319 depends on OR0_TRLX_NORMAL
320 bool "1 cycle"
321
322config OR0_CSCT_2_CYCLE
323 depends on OR0_TRLX_RELAXED
324 bool "2 cycles"
325
326config OR0_CSCT_4_CYCLE
327 depends on OR0_TRLX_NORMAL
328 bool "4 cycles"
329
330config OR0_CSCT_8_CYCLE
331 depends on OR0_TRLX_RELAXED
332 bool "8 cycles"
333
334endchoice
335
336choice
337 prompt "Command setup time"
338
339config OR0_CST_COINCIDENT
340 depends on OR0_TRLX_NORMAL
341 bool "Coincident with any command"
342
343config OR0_CST_QUARTER_CLOCK
344 depends on OR0_TRLX_NORMAL
345 bool "0.25 clocks after"
346
347config OR0_CST_HALF_CLOCK
348 depends on OR0_TRLX_RELAXED
349 bool "0.5 clocks after"
350
351config OR0_CST_ONE_CLOCK
352 depends on OR0_TRLX_RELAXED
353 bool "1 clock after"
354
355endchoice
356
357choice
358 prompt "Command hold time"
359
360config OR0_CHT_HALF_CLOCK
361 depends on OR0_TRLX_NORMAL
362 bool "0.5 clocks before"
363
364config OR0_CHT_ONE_CLOCK
365 depends on OR0_TRLX_NORMAL
366 bool "1 clock before"
367
368config OR0_CHT_ONE_HALF_CLOCK
369 depends on OR0_TRLX_RELAXED
370 bool "1.5 clocks before"
371
372config OR0_CHT_TWO_CLOCK
373 depends on OR0_TRLX_RELAXED
374 bool "2 clocks before"
375
376endchoice
377
378choice
379 prompt "Reset setup time"
380
381config OR0_RST_THREE_QUARTER_CLOCK
382 depends on OR0_TRLX_NORMAL
383 bool "0.75 clocks prior"
384
385config OR0_RST_ONE_HALF_CLOCK
386 depends on OR0_TRLX_RELAXED
387 bool "0.5 clocks prior"
388
389config OR0_RST_ONE_CLOCK
390 bool "1 clock prior"
391
392endchoice
393
394endif # BR0_MACHINE_FCM
395
396if BR0_MACHINE_UPM
397
398choice
399 prompt "Burst inhibit"
400
401config OR0_BI_BURSTSUPPORT
402 bool "Support burst access"
403
404config OR0_BI_BURSTINHIBIT
405 bool "Inhibit burst access"
406
407endchoice
408
409endif # BR0_MACHINE_UPM
410
411if BR0_MACHINE_SDRAM
412
413choice
414 prompt "Number of column address lines"
415
416config OR0_COLS_7
417 bool "7"
418
419config OR0_COLS_8
420 bool "8"
421
422config OR0_COLS_9
423 bool "9"
424
425config OR0_COLS_10
426 bool "10"
427
428config OR0_COLS_11
429 bool "11"
430
431config OR0_COLS_12
432 bool "12"
433
434config OR0_COLS_13
435 bool "13"
436
437config OR0_COLS_14
438 bool "14"
439
440endchoice
441
442choice
443 prompt "Number of rows address lines"
444
445config OR0_ROWS_9
446 bool "9"
447
448config OR0_ROWS_10
449 bool "10"
450
451config OR0_ROWS_11
452 bool "11"
453
454config OR0_ROWS_12
455 bool "12"
456
457config OR0_ROWS_13
458 bool "13"
459
460config OR0_ROWS_14
461 bool "14"
462
463config OR0_ROWS_15
464 bool "15"
465
466endchoice
467
468choice
469 prompt "Page mode select"
470
471config OR0_PMSEL_BTB
472 bool "Back-to-back"
473
474config OR0_PMSEL_KEPT_OPEN
475 bool "Page kept open until page miss or refresh"
476
477endchoice
478
479endif # BR0_MACHINE_SDRAM
480
481choice
482 prompt "Relaxed timing"
483
484config OR0_TRLX_NORMAL
485 bool "Normal"
486
487config OR0_TRLX_RELAXED
488 bool "Relaxed"
489
490endchoice
491
492choice
493 prompt "Extended hold time"
494
495config OR0_EHTR_NORMAL
496 depends on OR0_TRLX_NORMAL
497 bool "Normal"
498
499config OR0_EHTR_1_CYCLE
500 depends on OR0_TRLX_NORMAL
501 bool "1 idle clock cycle inserted"
502
503config OR0_EHTR_4_CYCLE
504 depends on OR0_TRLX_RELAXED
505 bool "4 idle clock cycles inserted"
506
507config OR0_EHTR_8_CYCLE
508 depends on OR0_TRLX_RELAXED
509 bool "8 idle clock cycles inserted"
510
511endchoice
512
513if !ARCH_MPC8308
514
515choice
516 prompt "External address latch delay"
517
518config OR0_EAD_NONE
519 bool "None"
520
521config OR0_EAD_EXTRA
522 bool "Extra"
523
524endchoice
525
526endif # !ARCH_MPC8308
527
528endif # ELBC_BR0_OR0
529
530config BR0_PORTSIZE
531 hex
532 default 0x800 if BR0_PORTSIZE_8BIT
533 default 0x1000 if BR0_PORTSIZE_16BIT
534 default 0x1800 if BR0_PORTSIZE_32BIT
535
536config BR0_ERRORCHECKING
537 hex
538 default 0x0 if !BR0_MACHINE_FCM
539 default 0x0 if BR0_ERRORCHECKING_DISABLED
540 default 0x200 if BR0_ERRORCHECKING_ECC_CHECKING
541 default 0x400 if BR0_ERRORCHECKING_BOTH
542
543config BR0_WRITE_PROTECT_BIT
544 hex
545 default 0x0 if !BR0_WRITE_PROTECT
546 default 0x100 if BR0_WRITE_PROTECT
547
548config BR0_MACHINE
549 hex
550 default 0x0 if BR0_MACHINE_GPCM
551 default 0x20 if BR0_MACHINE_FCM
552 default 0x60 if BR0_MACHINE_SDRAM
553 default 0x80 if BR0_MACHINE_UPMA
554 default 0xa0 if BR0_MACHINE_UPMB
555 default 0xc0 if BR0_MACHINE_UPMC
556
557config BR0_ATOMIC
558 hex
559 default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
560 default 0x0 if BR0_ATOMIC_NONE
561 default 0x4 if BR0_ATOMIC_RAWA
562 default 0x8 if BR0_ATOMIC_WARA
563
564config BR0_VALID_BIT
565 hex
566 default 0x0 if !ELBC_BR0_OR0
567 default 0x1 if ELBC_BR0_OR0
568
569config OR0_AM
570 hex
571 default 0xffff8000 if OR0_AM_32_KBYTES && !BR0_MACHINE_SDRAM
572 default 0xffff0000 if OR0_AM_64_KBYTES
573 default 0xfffe0000 if OR0_AM_128_KBYTES
574 default 0xfffc0000 if OR0_AM_256_KBYTES
575 default 0xfff80000 if OR0_AM_512_KBYTES
576 default 0xfff00000 if OR0_AM_1_MBYTES
577 default 0xffe00000 if OR0_AM_2_MBYTES
578 default 0xffc00000 if OR0_AM_4_MBYTES
579 default 0xff800000 if OR0_AM_8_MBYTES
580 default 0xff000000 if OR0_AM_16_MBYTES
581 default 0xfe000000 if OR0_AM_32_MBYTES
582 default 0xfc000000 if OR0_AM_64_MBYTES
583 default 0xf8000000 if OR0_AM_128_MBYTES
584 default 0xf0000000 if OR0_AM_256_MBYTES
585 default 0xe0000000 if OR0_AM_512_MBYTES
586 default 0xc0000000 if OR0_AM_1_GBYTES
587 default 0x80000000 if OR0_AM_2_GBYTES
588 default 0x00000000 if OR0_AM_4_GBYTES
589
590config OR0_XAM
591 hex
592 default 0x0 if !OR0_XAM_SET
593 default 0x6000 if OR0_XAM_SET
594
595config OR0_BCTLD
596 hex
597 default 0x0 if OR0_BCTLD_ASSERTED
598 default 0x1000 if OR0_BCTLD_NOT_ASSERTED
599
600config OR0_BI
601 hex
602 default 0x0 if !BR0_MACHINE_UPM
603 default 0x0 if OR0_BI_BURSTSUPPORT
604 default 0x100 if OR0_BI_BURSTINHIBIT
605
606config OR0_COLS
607 hex
608 default 0x0 if !BR0_MACHINE_SDRAM
609 default 0x0 if OR0_COLS_7
610 default 0x400 if OR0_COLS_8
611 default 0x800 if OR0_COLS_9
612 default 0xc00 if OR0_COLS_10
613 default 0x1000 if OR0_COLS_11
614 default 0x1400 if OR0_COLS_12
615 default 0x1800 if OR0_COLS_13
616 default 0x1c00 if OR0_COLS_14
617
618config OR0_ROWS
619 hex
620 default 0x0 if !BR0_MACHINE_SDRAM
621 default 0x0 if OR0_ROWS_9
622 default 0x40 if OR0_ROWS_10
623 default 0x80 if OR0_ROWS_11
624 default 0xc0 if OR0_ROWS_12
625 default 0x100 if OR0_ROWS_13
626 default 0x140 if OR0_ROWS_14
627 default 0x180 if OR0_ROWS_15
628
629config OR0_PMSEL
630 hex
631 default 0x0 if !BR0_MACHINE_SDRAM
632 default 0x0 if OR0_PMSEL_BTB
633 default 0x20 if OR0_PMSEL_KEPT_OPEN
634
635config OR0_SCY
636 hex
637 default 0x0 if !BR0_MACHINE_GPCM && !BR0_MACHINE_FCM
638 default 0x0 if OR0_SCY_0
639 default 0x10 if OR0_SCY_1
640 default 0x20 if OR0_SCY_2
641 default 0x30 if OR0_SCY_3
642 default 0x40 if OR0_SCY_4
643 default 0x50 if OR0_SCY_5
644 default 0x60 if OR0_SCY_6
645 default 0x70 if OR0_SCY_7
646 default 0x80 if OR0_SCY_8
647 default 0x90 if OR0_SCY_9
648 default 0xa0 if OR0_SCY_10
649 default 0xb0 if OR0_SCY_11
650 default 0xc0 if OR0_SCY_12
651 default 0xd0 if OR0_SCY_13
652 default 0xe0 if OR0_SCY_14
653 default 0xf0 if OR0_SCY_15
654
655config OR0_PGS
656 hex
657 default 0x0 if !BR0_MACHINE_FCM
658 default 0x0 if OR0_PGS_SMALL
659 default 0x400 if OR0_PGS_LARGE
660
661config OR0_CSCT
662 hex
663 default 0x0 if !BR0_MACHINE_FCM
664 default 0x0 if OR0_CSCT_1_CYCLE
665 default 0x0 if OR0_CSCT_2_CYCLE
666 default 0x200 if OR0_CSCT_4_CYCLE
667 default 0x200 if OR0_CSCT_8_CYCLE
668
669config OR0_CST
670 hex
671 default 0x0 if !BR0_MACHINE_FCM
672 default 0x0 if OR0_CST_COINCIDENT
673 default 0x100 if OR0_CST_QUARTER_CLOCK
674 default 0x0 if OR0_CST_HALF_CLOCK
675 default 0x100 if OR0_CST_ONE_CLOCK
676
677config OR0_CHT
678 hex
679 default 0x0 if !BR0_MACHINE_FCM
680 default 0x0 if OR0_CHT_HALF_CLOCK
681 default 0x80 if OR0_CHT_ONE_CLOCK
682 default 0x0 if OR0_CHT_ONE_HALF_CLOCK
683 default 0x80 if OR0_CHT_TWO_CLOCK
684
685config OR0_RST
686 hex
687 default 0x0 if !BR0_MACHINE_FCM
688 default 0x0 if OR0_RST_THREE_QUARTER_CLOCK
689 default 0x8 if OR0_RST_ONE_CLOCK
690 default 0x0 if OR0_RST_ONE_HALF_CLOCK
691
692config OR0_CSNT
693 hex
694 default 0x0 if !BR0_MACHINE_GPCM
695 default 0x0 if OR0_CSNT_NORMAL
696 default 0x800 if OR0_CSNT_EARLIER
697
698config OR0_ACS
699 hex
700 default 0x0 if !BR0_MACHINE_GPCM
701 default 0x0 if OR0_ACS_SAME_TIME
702 default 0x400 if OR0_ACS_QUARTER_CYCLE_EARLIER
703 default 0x600 if OR0_ACS_HALF_CYCLE_EARLIER
704
705config OR0_XACS
706 hex
707 default 0x0 if !BR0_MACHINE_GPCM
708 default 0x0 if OR0_XACS_NORMAL
709 default 0x100 if OR0_XACS_EXTENDED
710
711config OR0_SETA
712 hex
713 default 0x0 if !BR0_MACHINE_GPCM
714 default 0x0 if OR0_SETA_INTERNAL
715 default 0x8 if OR0_SETA_EXTERNAL
716
717config OR0_TRLX
718 hex
719 default 0x0 if OR0_TRLX_NORMAL
720 default 0x4 if OR0_TRLX_RELAXED
721
722config OR0_EHTR
723 hex
724 default 0x0 if OR0_EHTR_NORMAL
725 default 0x2 if OR0_EHTR_1_CYCLE
726 default 0x0 if OR0_EHTR_4_CYCLE
727 default 0x2 if OR0_EHTR_8_CYCLE
728
729config OR0_EAD
730 hex
731 default 0x0 if ARCH_MPC8308
732 default 0x0 if OR0_EAD_NONE
733 default 0x1 if OR0_EAD_EXTRA