blob: 5b0b86b39bee833201a6fdf23c4d0b2a2b4b37fb [file] [log] [blame]
Yuantian Tang92f18ff2019-04-10 16:43:34 +08001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
Yangbo Lubb32e682021-06-03 10:51:19 +08003 * Copyright 2019-2021 NXP
Yuantian Tang92f18ff2019-04-10 16:43:34 +08004 */
5
6#ifndef __L1028A_COMMON_H
7#define __L1028A_COMMON_H
8
Yuantian Tang92f18ff2019-04-10 16:43:34 +08009#include <asm/arch/stream_id_lsch3.h>
10#include <asm/arch/config.h>
11#include <asm/arch/soc.h>
12
13/* Link Definitions */
Yuantian Tang92f18ff2019-04-10 16:43:34 +080014
Yuantian Tang92f18ff2019-04-10 16:43:34 +080015#define CONFIG_VERY_BIG_RAM
16#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
17#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
18#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
19#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
20#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
21
Yuantian Tang92f18ff2019-04-10 16:43:34 +080022/*
23 * SMP Definitinos
24 */
Michael Wallef056e0f2020-06-01 21:53:26 +020025#define CPU_RELEASE_ADDR secondary_boot_addr
Yuantian Tang92f18ff2019-04-10 16:43:34 +080026
Biwen Lie7c3b042021-02-05 19:01:57 +080027/* GPIO */
Biwen Lie7c3b042021-02-05 19:01:57 +080028
Yuantian Tang92f18ff2019-04-10 16:43:34 +080029/* I2C */
Yuantian Tang92f18ff2019-04-10 16:43:34 +080030
31/* Serial Port */
Yuantian Tang92f18ff2019-04-10 16:43:34 +080032#define CONFIG_SYS_NS16550_SERIAL
33#define CONFIG_SYS_NS16550_REG_SIZE 1
34#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
35
Yuantian Tang92f18ff2019-04-10 16:43:34 +080036/* Miscellaneous configurable options */
Yuantian Tang92f18ff2019-04-10 16:43:34 +080037
38/* Physical Memory Map */
Yuantian Tang92f18ff2019-04-10 16:43:34 +080039
40#define CONFIG_HWCONFIG
41#define HWCONFIG_BUFFER_SIZE 128
42
Yuantian Tang92f18ff2019-04-10 16:43:34 +080043#define BOOT_TARGET_DEVICES(func) \
44 func(MMC, mmc, 0) \
Yuantian Tang7f3da7b2019-11-04 15:10:45 +080045 func(MMC, mmc, 1) \
Yuantian Tang7a224e72020-03-10 11:31:05 +080046 func(USB, usb, 0) \
47 func(DHCP, dhcp, na)
Yuantian Tang92f18ff2019-04-10 16:43:34 +080048#include <config_distro_bootcmd.h>
49
Yuantian Tang7f3da7b2019-11-04 15:10:45 +080050#define XSPI_NOR_BOOTCOMMAND \
51 "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
52 "env exists secureboot && esbc_halt;;"
Yuantian Tang92f18ff2019-04-10 16:43:34 +080053#define SD_BOOTCOMMAND \
Yuantian Tang7f3da7b2019-11-04 15:10:45 +080054 "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
55 "env exists secureboot && esbc_halt;"
56#define SD2_BOOTCOMMAND \
57 "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
Yuantian Tang92f18ff2019-04-10 16:43:34 +080058 "env exists secureboot && esbc_halt;"
59
Yuantian Tang92f18ff2019-04-10 16:43:34 +080060#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
61
Yuantian Tang92f18ff2019-04-10 16:43:34 +080062#define OCRAM_NONSECURE_SIZE 0x00010000
Yuantian Tang92f18ff2019-04-10 16:43:34 +080063#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
Yuantian Tang92f18ff2019-04-10 16:43:34 +080064
Yuantian Tang92f18ff2019-04-10 16:43:34 +080065/* I2C bus multiplexer */
66#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
67#define I2C_MUX_CH_DEFAULT 0x8
68
69/* EEPROM */
Yuantian Tang92f18ff2019-04-10 16:43:34 +080070#define CONFIG_SYS_I2C_EEPROM_NXID
71#define CONFIG_SYS_EEPROM_BUS_NUM 0
Yuantian Tang92f18ff2019-04-10 16:43:34 +080072
Wen He41e63db2019-11-18 13:26:09 +080073/* DisplayPort */
74#define DP_PWD_EN_DEFAULT_MASK 0x8
75
Udit Agarwal22ec2382019-11-07 16:11:32 +000076#ifdef CONFIG_NXP_ESBC
Yuantian Tang029d8ab2019-05-24 14:36:27 +080077#include <asm/fsl_secure_boot.h>
78#endif
79
Yuantian Tang92f18ff2019-04-10 16:43:34 +080080#endif /* __L1028A_COMMON_H */