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Stefan Roese326c9712005-08-01 16:41:48 +02001/*
Stefan Roeseb1669da2007-01-30 17:04:19 +01002 * (C) Copyright 2005-2007
Stefan Roese1d026382005-08-11 18:03:14 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
Stefan Roese326c9712005-08-01 16:41:48 +02004 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese326c9712005-08-01 16:41:48 +02006 */
7
8/************************************************************************
Stefan Roeseb1669da2007-01-30 17:04:19 +01009 * yosemite.h - configuration for Yosemite & Yellowstone boards
Stefan Roese326c9712005-08-01 16:41:48 +020010 ***********************************************************************/
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*-----------------------------------------------------------------------
15 * High Level Configuration Options
16 *----------------------------------------------------------------------*/
Stefan Roeseb1669da2007-01-30 17:04:19 +010017/* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/
18#ifndef CONFIG_YELLOWSTONE
Stefan Roeseb1669da2007-01-30 17:04:19 +010019#define CONFIG_440EP 1 /* Specific PPC440EP support */
20#define CONFIG_HOSTNAME yosemite
21#else
22#define CONFIG_440GR 1 /* Specific PPC440GR support */
23#define CONFIG_HOSTNAME yellowstone
24#endif
Grzegorz Bernacki837bc5b2007-06-15 11:19:28 +020025#define CONFIG_440 1 /* ... PPC440 family */
Stefan Roese326c9712005-08-01 16:41:48 +020026#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
27
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020028#define CONFIG_SYS_TEXT_BASE 0xFFF80000
29
Stefan Roesecfe58022008-06-06 15:55:21 +020030/*
31 * Include common defines/options for all AMCC eval boards
32 */
33#include "amcc-common.h"
34
Stefan Roese1d026382005-08-11 18:03:14 +020035#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
Stefan Roese03687752006-10-07 11:30:52 +020036#define CONFIG_BOARD_RESET 1 /* call board_reset() */
Stefan Roese1d026382005-08-11 18:03:14 +020037
Stefan Roese326c9712005-08-01 16:41:48 +020038/*-----------------------------------------------------------------------
39 * Base addresses -- Note these are effective addresses where the
40 * actual resources get mapped (not physical addresses)
41 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020042#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
43#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
44#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
45#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
46#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
Stefan Roese326c9712005-08-01 16:41:48 +020047
48/*Don't change either of these*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020049#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
Stefan Roese326c9712005-08-01 16:41:48 +020050/*Don't change either of these*/
51
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020052#define CONFIG_SYS_USB_DEVICE 0x50000000
53#define CONFIG_SYS_NVRAM_BASE_ADDR 0x80000000
54#define CONFIG_SYS_BCSR_BASE (CONFIG_SYS_NVRAM_BASE_ADDR | 0x2000)
55#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
Stefan Roese326c9712005-08-01 16:41:48 +020056
57/*-----------------------------------------------------------------------
58 * Initial RAM & stack pointer (placed in SDRAM)
59 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020060#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
61#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +020062#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Wolfgang Denk0191e472010-10-26 14:34:52 +020063#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese326c9712005-08-01 16:41:48 +020065
Stefan Roese326c9712005-08-01 16:41:48 +020066/*-----------------------------------------------------------------------
67 * Serial Port
68 *----------------------------------------------------------------------*/
Stefan Roese3ddce572010-09-20 16:05:31 +020069#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020070#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
Stefan Roese326c9712005-08-01 16:41:48 +020071
Stefan Roese326c9712005-08-01 16:41:48 +020072/*-----------------------------------------------------------------------
Stefan Roese1d026382005-08-11 18:03:14 +020073 * Environment
Stefan Roese326c9712005-08-01 16:41:48 +020074 *----------------------------------------------------------------------*/
Stefan Roese1d026382005-08-11 18:03:14 +020075/*
76 * Define here the location of the environment variables (FLASH or EEPROM).
77 * Note: DENX encourages to use redundant environment in FLASH.
78 */
79#if 1
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020080#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese1d026382005-08-11 18:03:14 +020081#else
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +020082#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Stefan Roese1d026382005-08-11 18:03:14 +020083#endif
Stefan Roese326c9712005-08-01 16:41:48 +020084
85/*-----------------------------------------------------------------------
86 * FLASH related
87 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020088#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +020089#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020090#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
Stefan Roese326c9712005-08-01 16:41:48 +020091
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020092#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
93#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roese326c9712005-08-01 16:41:48 +020094
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020095#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
96#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese326c9712005-08-01 16:41:48 +020097
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
Stefan Roese31c9ee72006-05-10 15:06:58 +020099
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200100#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese1d026382005-08-11 18:03:14 +0200101
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200102#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200103#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200105#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roese1d026382005-08-11 18:03:14 +0200106
107/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200108#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
109#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200110#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roese326c9712005-08-01 16:41:48 +0200111
112/*-----------------------------------------------------------------------
113 * DDR SDRAM
114 *----------------------------------------------------------------------*/
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200115#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */
117#define CONFIG_SYS_SDRAM_BANKS (2)
Stefan Roese1d026382005-08-11 18:03:14 +0200118
Ira Snyder4dbd9762008-04-29 11:18:54 -0700119/*-----------------------------------------------------------------------
Stefan Roese326c9712005-08-01 16:41:48 +0200120 * I2C
121 *----------------------------------------------------------------------*/
Dirk Eibach42b204f2013-04-25 02:40:01 +0000122#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Stefan Roese326c9712005-08-01 16:41:48 +0200123
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200124#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
125#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
126#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
127#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese326c9712005-08-01 16:41:48 +0200128
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +0200129#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200130#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */
131#define CONFIG_ENV_OFFSET 0x0
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +0200132#endif /* CONFIG_ENV_IS_IN_EEPROM */
Stefan Roese1d026382005-08-11 18:03:14 +0200133
Stefan Roesea05ed2d2007-12-04 16:29:48 +0100134/* I2C SYSMON (LM75, AD7414 is almost compatible) */
135#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
136#define CONFIG_DTT_AD7414 1 /* use AD7414 */
137#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_DTT_MAX_TEMP 70
139#define CONFIG_SYS_DTT_LOW_TEMP -30
140#define CONFIG_SYS_DTT_HYSTERESIS 3
Stefan Roesea05ed2d2007-12-04 16:29:48 +0100141
Stefan Roesecfe58022008-06-06 15:55:21 +0200142/*
143 * Default environment variables
144 */
Stefan Roese1d026382005-08-11 18:03:14 +0200145#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roesecfe58022008-06-06 15:55:21 +0200146 CONFIG_AMCC_DEF_ENV \
147 CONFIG_AMCC_DEF_ENV_POWERPC \
148 CONFIG_AMCC_DEF_ENV_PPC_OLD \
149 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese1d026382005-08-11 18:03:14 +0200150 "kernel_addr=fc000000\0" \
Stefan Roese3b07aeb2006-05-15 15:11:20 +0200151 "ramdisk_addr=fc180000\0" \
Stefan Roese1d026382005-08-11 18:03:14 +0200152 ""
Stefan Roese326c9712005-08-01 16:41:48 +0200153
Ira Snyder4dbd9762008-04-29 11:18:54 -0700154#define CONFIG_HAS_ETH0 1 /* add support for "ethaddr" */
Stefan Roese326c9712005-08-01 16:41:48 +0200155#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
156#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
Stefan Roesecfe58022008-06-06 15:55:21 +0200157#define CONFIG_PHY1_ADDR 3
Stefan Roese326c9712005-08-01 16:41:48 +0200158
159/* Partitions */
Stefan Roese326c9712005-08-01 16:41:48 +0200160
Stefan Roeseb30f2a12005-08-08 12:42:22 +0200161#ifdef CONFIG_440EP
Stefan Roese326c9712005-08-01 16:41:48 +0200162/* USB */
Markus Klotzbuecher43c8b312006-11-27 11:44:58 +0100163#define CONFIG_USB_OHCI_NEW
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200164#define CONFIG_SYS_OHCI_BE_CONTROLLER
Stefan Roese326c9712005-08-01 16:41:48 +0200165
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200166#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
167#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
168#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_PERIPHERAL_BASE | 0x1000)
169#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
170#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
Markus Klotzbuecher661ffe52006-11-27 11:43:09 +0100171
Stefan Roeseb1669da2007-01-30 17:04:19 +0100172/* Comment this out to enable USB 1.1 device */
Stefan Roese326c9712005-08-01 16:41:48 +0200173#define USB_2_0_DEVICE
Stefan Roeseb1669da2007-01-30 17:04:19 +0100174
Stefan Roeseb1669da2007-01-30 17:04:19 +0100175#define CONFIG_SUPPORT_VFAT
Stefan Roeseb1669da2007-01-30 17:04:19 +0100176#endif /* CONFIG_440EP */
Stefan Roese326c9712005-08-01 16:41:48 +0200177
178#ifdef DEBUG
179#define CONFIG_PANIC_HANG
180#else
181#define CONFIG_HW_WATCHDOG /* watchdog */
182#endif
183
Jon Loeliger03bfcb92007-07-04 22:33:46 -0500184/*
Stefan Roesecfe58022008-06-06 15:55:21 +0200185 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger5c4ddae2007-07-10 10:12:10 -0500186 */
Stefan Roesea05ed2d2007-12-04 16:29:48 +0100187#define CONFIG_CMD_DTT
Jon Loeliger03bfcb92007-07-04 22:33:46 -0500188#define CONFIG_CMD_PCI
Stefan Roese764784c2005-10-14 15:37:34 +0200189
Jon Loeliger03bfcb92007-07-04 22:33:46 -0500190#ifdef CONFIG_440EP
Jon Loeliger03bfcb92007-07-04 22:33:46 -0500191#endif
Stefan Roese326c9712005-08-01 16:41:48 +0200192
Stefan Roese326c9712005-08-01 16:41:48 +0200193/*-----------------------------------------------------------------------
194 * PCI stuff
195 *-----------------------------------------------------------------------
196 */
197/* General PCI */
Gabor Juhosb4458732013-05-30 07:06:12 +0000198#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roese1d026382005-08-11 18:03:14 +0200199#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200200#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
Stefan Roese326c9712005-08-01 16:41:48 +0200201
202/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200203#define CONFIG_SYS_PCI_TARGET_INIT
204#define CONFIG_SYS_PCI_MASTER_INIT
Stefan Roese326c9712005-08-01 16:41:48 +0200205
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
207#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
Stefan Roese326c9712005-08-01 16:41:48 +0200208
Stefan Roese326c9712005-08-01 16:41:48 +0200209/*-----------------------------------------------------------------------
Stefan Roesec0958942007-01-13 07:59:19 +0100210 * External Bus Controller (EBC) Setup
211 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
213#define CONFIG_SYS_CPLD 0x80000000
Stefan Roesec0958942007-01-13 07:59:19 +0100214
215/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216#define CONFIG_SYS_EBC_PB0AP 0x03017300
217#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000)
Stefan Roesec0958942007-01-13 07:59:19 +0100218
219/* Memory Bank 2 (CPLD) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200220#define CONFIG_SYS_EBC_PB2AP 0x04814500
221#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD | 0x18000)
Stefan Roesec0958942007-01-13 07:59:19 +0100222
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200223#define CONFIG_SYS_BCSR5_PCI66EN 0x80
Stefan Roesefa257472007-10-15 11:29:33 +0200224
Stefan Roese326c9712005-08-01 16:41:48 +0200225#endif /* __CONFIG_H */