Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 1 | CONFIG_ARM=y |
Peng Fan | c8a61c0 | 2022-04-13 17:47:20 +0800 | [diff] [blame] | 2 | CONFIG_COUNTER_FREQUENCY=25000000 |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 3 | CONFIG_TARGET_SL28=y |
Tom Rini | e25a03a | 2021-11-01 12:19:22 +0000 | [diff] [blame] | 4 | CONFIG_SYS_MALLOC_LEN=0x202000 |
| 5 | CONFIG_SYS_MALLOC_F_LEN=0x4000 |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 6 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 7 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 8 | CONFIG_NR_DRAM_BANKS=2 |
| 9 | CONFIG_ENV_SIZE=0x2000 |
| 10 | CONFIG_ENV_OFFSET=0x3e0000 |
| 11 | CONFIG_ENV_SECT_SIZE=0x10000 |
Tom Rini | a20e51f | 2021-06-28 10:17:29 -0400 | [diff] [blame] | 12 | CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28" |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 13 | CONFIG_SPL_TEXT_BASE=0x18010000 |
| 14 | CONFIG_SYS_FSL_SDHC_CLK_DIV=1 |
Simon Glass | f4d6039 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 15 | CONFIG_SPL_SERIAL=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 16 | CONFIG_SPL_SIZE_LIMIT=0x20000 |
| 17 | CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0 |
| 18 | CONFIG_SPL=y |
| 19 | CONFIG_ENV_OFFSET_REDUND=0x3f0000 |
| 20 | CONFIG_SPL_SPI_FLASH_SUPPORT=y |
Simon Glass | a582047 | 2021-08-08 12:20:14 -0600 | [diff] [blame] | 21 | CONFIG_SPL_SPI=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 22 | # CONFIG_PSCI_RESET is not set |
Michael Walle | 187bae9 | 2022-04-25 09:25:08 +0530 | [diff] [blame] | 23 | CONFIG_ARMV8_PSCI=y |
| 24 | CONFIG_ARMV8_PSCI_RELOCATE=y |
Tom Rini | 4b2fcb3 | 2022-04-08 13:36:51 -0400 | [diff] [blame] | 25 | CONFIG_SYS_LOAD_ADDR=0x82000000 |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 26 | CONFIG_AHCI=y |
| 27 | CONFIG_DISTRO_DEFAULTS=y |
Tom Rini | 4ddbade | 2022-05-25 12:16:03 -0400 | [diff] [blame] | 28 | CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y |
| 29 | CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800eff0 |
Tom Rini | 5ca768d | 2022-01-24 21:08:41 +0000 | [diff] [blame] | 30 | CONFIG_MP=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 31 | CONFIG_FIT=y |
| 32 | CONFIG_SPL_LOAD_FIT=y |
| 33 | # CONFIG_USE_SPL_FIT_GENERATOR is not set |
| 34 | CONFIG_OF_BOARD_SETUP=y |
| 35 | CONFIG_OF_STDOUT_VIA_ALIAS=y |
| 36 | CONFIG_BOOTDELAY=10 |
| 37 | CONFIG_USE_BOOTARGS=y |
| 38 | CONFIG_BOARD_LATE_INIT=y |
| 39 | CONFIG_PCI_INIT_R=y |
Tom Rini | abb0f52 | 2022-05-16 17:20:26 -0400 | [diff] [blame] | 40 | CONFIG_SPL_MAX_SIZE=0x20000 |
Tom Rini | 65aa124 | 2022-05-27 10:19:45 -0400 | [diff] [blame] | 41 | CONFIG_SPL_HAS_BSS_LINKER_SECTION=y |
| 42 | CONFIG_SPL_BSS_START_ADDR=0x80100000 |
Tom Rini | 0cb89e7 | 2022-05-19 15:09:22 -0400 | [diff] [blame] | 43 | CONFIG_SPL_BSS_MAX_SIZE=0x100000 |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 44 | CONFIG_SPL_BOARD_INIT=y |
Tom Rini | 8a14ac4 | 2022-05-26 13:13:21 -0400 | [diff] [blame] | 45 | # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set |
| 46 | CONFIG_SPL_STACK=0x18009ff0 |
Tom Rini | 166e322 | 2022-05-27 12:48:32 -0400 | [diff] [blame] | 47 | CONFIG_SYS_SPL_MALLOC=y |
Simon Glass | 6457106 | 2021-08-08 12:20:16 -0600 | [diff] [blame] | 48 | CONFIG_SPL_MPC8XXX_INIT_DDR=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 49 | CONFIG_SPL_SPI_LOAD=y |
Tom Rini | e22fa4f | 2021-08-10 15:08:46 -0400 | [diff] [blame] | 50 | CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000 |
Tom Rini | ae17fa3 | 2022-05-11 18:01:06 -0400 | [diff] [blame] | 51 | CONFIG_SYS_CBSIZE=256 |
Tom Rini | cbfa139 | 2022-05-11 17:38:09 -0400 | [diff] [blame] | 52 | CONFIG_SYS_PBSIZE=276 |
Tom Rini | f3c2f99 | 2022-06-25 19:29:46 -0400 | [diff] [blame] | 53 | CONFIG_SYS_BOOTM_LEN=0x800000 |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 54 | CONFIG_CMD_ASKENV=y |
| 55 | CONFIG_CMD_GREPENV=y |
| 56 | CONFIG_CMD_NVEDIT_EFI=y |
Michael Walle | e449f35 | 2021-10-15 15:15:25 +0200 | [diff] [blame] | 57 | CONFIG_CMD_DFU=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 58 | CONFIG_CMD_DM=y |
Michael Walle | 7832e17 | 2021-11-15 23:45:47 +0100 | [diff] [blame] | 59 | CONFIG_CMD_GPIO=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 60 | CONFIG_CMD_GPT=y |
| 61 | CONFIG_CMD_I2C=y |
| 62 | CONFIG_CMD_MMC=y |
| 63 | CONFIG_CMD_PCI=y |
| 64 | CONFIG_CMD_USB=y |
Michael Walle | e449f35 | 2021-10-15 15:15:25 +0200 | [diff] [blame] | 65 | CONFIG_CMD_USB_MASS_STORAGE=y |
Michael Walle | 7832e17 | 2021-11-15 23:45:47 +0100 | [diff] [blame] | 66 | CONFIG_CMD_WDT=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 67 | CONFIG_CMD_CACHE=y |
| 68 | CONFIG_CMD_EFIDEBUG=y |
| 69 | CONFIG_CMD_RNG=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 70 | CONFIG_OF_CONTROL=y |
| 71 | CONFIG_SPL_OF_CONTROL=y |
Michael Walle | fb55906 | 2022-02-25 18:21:56 +0530 | [diff] [blame] | 72 | CONFIG_OF_LIST="fsl-ls1028a-kontron-sl28 fsl-ls1028a-kontron-sl28-var1 fsl-ls1028a-kontron-sl28-var2 fsl-ls1028a-kontron-sl28-var3 fsl-ls1028a-kontron-sl28-var4" |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 73 | CONFIG_ENV_OVERWRITE=y |
| 74 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 75 | CONFIG_SYS_REDUNDAND_ENVIRONMENT=y |
Tom Rini | f9d5e83 | 2022-03-18 08:38:25 -0400 | [diff] [blame] | 76 | CONFIG_SYS_RX_ETH_BUFFER=8 |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 77 | CONFIG_SPL_DM_SEQ_ALIAS=y |
Simon Glass | 701ef06 | 2022-01-31 07:49:33 -0700 | [diff] [blame] | 78 | CONFIG_SATA=y |
Tom Rini | f4e64b9 | 2022-02-08 23:50:55 +0000 | [diff] [blame] | 79 | CONFIG_SCSI_AHCI=y |
Michael Walle | 101410e | 2021-01-08 00:08:59 +0100 | [diff] [blame] | 80 | CONFIG_SATA_CEVA=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 81 | CONFIG_FSL_CAAM=y |
| 82 | CONFIG_SYS_FSL_DDR3=y |
Tom Rini | 468c2d5 | 2021-08-21 13:50:18 -0400 | [diff] [blame] | 83 | CONFIG_DDR_ECC=y |
| 84 | CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y |
Michael Walle | 0b13209 | 2021-11-09 14:48:51 +0530 | [diff] [blame] | 85 | CONFIG_DFU_MMC=y |
| 86 | CONFIG_DFU_SF=y |
Michael Walle | 7832e17 | 2021-11-15 23:45:47 +0100 | [diff] [blame] | 87 | CONFIG_SL28CPLD_GPIO=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 88 | CONFIG_I2C_SET_DEFAULT_BUS_NUM=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 89 | CONFIG_I2C_MUX=y |
Michael Walle | 7832e17 | 2021-11-15 23:45:47 +0100 | [diff] [blame] | 90 | CONFIG_SL28CPLD=y |
Michael Walle | 44804c0 | 2021-03-17 15:01:38 +0100 | [diff] [blame] | 91 | CONFIG_MMC_HS400_SUPPORT=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 92 | CONFIG_FSL_ESDHC=y |
| 93 | CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y |
Michael Walle | 2fcd04d | 2020-12-09 10:53:26 +0100 | [diff] [blame] | 94 | # CONFIG_SPI_FLASH_UNLOCK_ALL is not set |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 95 | CONFIG_SPI_FLASH_WINBOND=y |
| 96 | # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set |
| 97 | CONFIG_PHYLIB=y |
| 98 | CONFIG_PHY_ATHEROS=y |
Tom Rini | b1607c8 | 2021-03-02 09:36:23 -0500 | [diff] [blame] | 99 | CONFIG_PHY_FIXED=y |
Tom Rini | b1607c8 | 2021-03-02 09:36:23 -0500 | [diff] [blame] | 100 | CONFIG_DM_DSA=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 101 | CONFIG_PHY_GIGE=y |
| 102 | CONFIG_E1000=y |
Alex Marginean | e068a48 | 2021-01-25 14:23:57 +0200 | [diff] [blame] | 103 | CONFIG_MSCC_FELIX_SWITCH=y |
Mark Kettenis | f8463d6 | 2022-01-22 20:38:11 +0100 | [diff] [blame] | 104 | CONFIG_NVME_PCI=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 105 | CONFIG_PCIE_ECAM_GENERIC=y |
| 106 | CONFIG_PCIE_LAYERSCAPE_RC=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 107 | CONFIG_RTC_RV8803=y |
| 108 | CONFIG_SCSI=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 109 | CONFIG_SYS_NS16550=y |
| 110 | CONFIG_SPI=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 111 | CONFIG_FSL_DSPI=y |
| 112 | CONFIG_NXP_FSPI=y |
| 113 | CONFIG_USB=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 114 | # CONFIG_SPL_DM_USB is not set |
Michael Walle | e449f35 | 2021-10-15 15:15:25 +0200 | [diff] [blame] | 115 | CONFIG_DM_USB_GADGET=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 116 | CONFIG_USB_XHCI_HCD=y |
Michael Walle | f55d4cc | 2021-10-15 15:15:24 +0200 | [diff] [blame] | 117 | # CONFIG_USB_XHCI_FSL is not set |
| 118 | CONFIG_USB_DWC3=y |
| 119 | CONFIG_USB_DWC3_LAYERSCAPE=y |
Michael Walle | e449f35 | 2021-10-15 15:15:25 +0200 | [diff] [blame] | 120 | CONFIG_USB_GADGET=y |
| 121 | CONFIG_USB_GADGET_DOWNLOAD=y |
Michael Walle | 7832e17 | 2021-11-15 23:45:47 +0100 | [diff] [blame] | 122 | # CONFIG_WATCHDOG is not set |
| 123 | # CONFIG_WATCHDOG_AUTOSTART is not set |
| 124 | CONFIG_WDT=y |
| 125 | CONFIG_WDT_SL28CPLD=y |
Michael Walle | 05deab5 | 2021-11-15 23:45:48 +0100 | [diff] [blame] | 126 | CONFIG_WDT_SP805=y |
Michael Walle | 36ba764 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 127 | CONFIG_OF_LIBFDT_ASSUME_MASK=0x0 |
| 128 | CONFIG_OF_LIBFDT_OVERLAY=y |
Michael Walle | 54700a2 | 2021-09-29 13:39:09 +0200 | [diff] [blame] | 129 | CONFIG_EFI_SET_TIME=y |
Michael Walle | 0b13209 | 2021-11-09 14:48:51 +0530 | [diff] [blame] | 130 | CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y |
Michael Walle | 0b13209 | 2021-11-09 14:48:51 +0530 | [diff] [blame] | 131 | CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y |