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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andy Flemingad347bb2008-10-30 16:41:01 -05002/*
3 * Copyright 2008, Freescale Semiconductor, Inc
4 * Andy Fleming
5 *
6 * Based vaguely on the Linux code
Andy Flemingad347bb2008-10-30 16:41:01 -05007 */
8
9#include <config.h>
10#include <common.h>
11#include <command.h>
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -060012#include <dm.h>
13#include <dm/device-internal.h>
Stephen Warrenbf0c7852014-05-23 12:47:06 -060014#include <errno.h>
Andy Flemingad347bb2008-10-30 16:41:01 -050015#include <mmc.h>
16#include <part.h>
Peng Fan15305962016-10-11 15:08:43 +080017#include <power/regulator.h>
Andy Flemingad347bb2008-10-30 16:41:01 -050018#include <malloc.h>
Simon Glass2dd337a2015-09-02 17:24:58 -060019#include <memalign.h>
Andy Flemingad347bb2008-10-30 16:41:01 -050020#include <linux/list.h>
Rabin Vincent69d4e2c2009-04-05 13:30:54 +053021#include <div64.h>
Paul Burton8d30cc92013-09-09 15:30:26 +010022#include "mmc_private.h"
Andy Flemingad347bb2008-10-30 16:41:01 -050023
Kishon Vijay Abraham I4afb12b2017-09-21 16:30:00 +020024static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +020025static int mmc_power_cycle(struct mmc *mmc);
Marek Vasuta318a7a2018-04-15 00:37:11 +020026#if !CONFIG_IS_ENABLED(MMC_TINY)
Jean-Jacques Hiblot3d30972b2017-09-21 16:30:09 +020027static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
Marek Vasutf537e392016-12-01 02:06:33 +010028#endif
Marek Vasutf537e392016-12-01 02:06:33 +010029
Simon Glasseba48f92017-07-29 11:35:31 -060030#if !CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +020031
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +010032#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +020033static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
34{
35 return -ENOSYS;
36}
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +010037#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +020038
Jeroen Hofsteeaedeeaa2014-07-12 21:24:08 +020039__weak int board_mmc_getwp(struct mmc *mmc)
Nikita Kiryanov020f2612012-12-03 02:19:46 +000040{
41 return -1;
42}
43
44int mmc_getwp(struct mmc *mmc)
45{
46 int wp;
47
48 wp = board_mmc_getwp(mmc);
49
Peter Korsgaardf7b15102013-03-21 04:00:03 +000050 if (wp < 0) {
Pantelis Antoniou2c850462014-03-11 19:34:20 +020051 if (mmc->cfg->ops->getwp)
52 wp = mmc->cfg->ops->getwp(mmc);
Peter Korsgaardf7b15102013-03-21 04:00:03 +000053 else
54 wp = 0;
55 }
Nikita Kiryanov020f2612012-12-03 02:19:46 +000056
57 return wp;
58}
59
Jeroen Hofstee47726302014-07-10 22:46:28 +020060__weak int board_mmc_getcd(struct mmc *mmc)
61{
Stefano Babic6e00edf2010-02-05 15:04:43 +010062 return -1;
63}
Simon Glass394dfc02016-06-12 23:30:22 -060064#endif
Stefano Babic6e00edf2010-02-05 15:04:43 +010065
Simon Glassb23d96e2016-06-12 23:30:20 -060066#ifdef CONFIG_MMC_TRACE
67void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
Andy Flemingad347bb2008-10-30 16:41:01 -050068{
Simon Glassb23d96e2016-06-12 23:30:20 -060069 printf("CMD_SEND:%d\n", cmd->cmdidx);
70 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
71}
Marek Vasutdccb6082012-03-15 18:41:35 +000072
Simon Glassb23d96e2016-06-12 23:30:20 -060073void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
74{
Raffaele Recalcati894b1e22011-03-11 02:01:14 +000075 int i;
76 u8 *ptr;
77
Bin Meng8d1ad1e2016-03-17 21:53:14 -070078 if (ret) {
79 printf("\t\tRET\t\t\t %d\n", ret);
80 } else {
81 switch (cmd->resp_type) {
82 case MMC_RSP_NONE:
83 printf("\t\tMMC_RSP_NONE\n");
84 break;
85 case MMC_RSP_R1:
86 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
87 cmd->response[0]);
88 break;
89 case MMC_RSP_R1b:
90 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
91 cmd->response[0]);
92 break;
93 case MMC_RSP_R2:
94 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
95 cmd->response[0]);
96 printf("\t\t \t\t 0x%08X \n",
97 cmd->response[1]);
98 printf("\t\t \t\t 0x%08X \n",
99 cmd->response[2]);
100 printf("\t\t \t\t 0x%08X \n",
101 cmd->response[3]);
Raffaele Recalcati894b1e22011-03-11 02:01:14 +0000102 printf("\n");
Bin Meng8d1ad1e2016-03-17 21:53:14 -0700103 printf("\t\t\t\t\tDUMPING DATA\n");
104 for (i = 0; i < 4; i++) {
105 int j;
106 printf("\t\t\t\t\t%03d - ", i*4);
107 ptr = (u8 *)&cmd->response[i];
108 ptr += 3;
109 for (j = 0; j < 4; j++)
110 printf("%02X ", *ptr--);
111 printf("\n");
112 }
113 break;
114 case MMC_RSP_R3:
115 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
116 cmd->response[0]);
117 break;
118 default:
119 printf("\t\tERROR MMC rsp not supported\n");
120 break;
Bin Meng4a4ef872016-03-17 21:53:13 -0700121 }
Raffaele Recalcati894b1e22011-03-11 02:01:14 +0000122 }
Simon Glassb23d96e2016-06-12 23:30:20 -0600123}
124
125void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
126{
127 int status;
128
129 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
130 printf("CURR STATE:%d\n", status);
131}
Raffaele Recalcati894b1e22011-03-11 02:01:14 +0000132#endif
Simon Glassb23d96e2016-06-12 23:30:20 -0600133
Jean-Jacques Hiblota94fb412017-09-21 16:29:53 +0200134#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
135const char *mmc_mode_name(enum bus_mode mode)
136{
137 static const char *const names[] = {
138 [MMC_LEGACY] = "MMC legacy",
139 [SD_LEGACY] = "SD Legacy",
140 [MMC_HS] = "MMC High Speed (26MHz)",
141 [SD_HS] = "SD High Speed (50MHz)",
142 [UHS_SDR12] = "UHS SDR12 (25MHz)",
143 [UHS_SDR25] = "UHS SDR25 (50MHz)",
144 [UHS_SDR50] = "UHS SDR50 (100MHz)",
145 [UHS_SDR104] = "UHS SDR104 (208MHz)",
146 [UHS_DDR50] = "UHS DDR50 (50MHz)",
147 [MMC_HS_52] = "MMC High Speed (52MHz)",
148 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
149 [MMC_HS_200] = "HS200 (200MHz)",
Peng Fan46801252018-08-10 14:07:54 +0800150 [MMC_HS_400] = "HS400 (200MHz)",
Jean-Jacques Hiblota94fb412017-09-21 16:29:53 +0200151 };
152
153 if (mode >= MMC_MODES_END)
154 return "Unknown mode";
155 else
156 return names[mode];
157}
158#endif
159
Jean-Jacques Hiblot78422312017-09-21 16:29:55 +0200160static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
161{
162 static const int freqs[] = {
Jaehoon Chung7c5c7302018-01-30 14:10:16 +0900163 [MMC_LEGACY] = 25000000,
Jean-Jacques Hiblot78422312017-09-21 16:29:55 +0200164 [SD_LEGACY] = 25000000,
165 [MMC_HS] = 26000000,
166 [SD_HS] = 50000000,
Jaehoon Chung7c5c7302018-01-30 14:10:16 +0900167 [MMC_HS_52] = 52000000,
168 [MMC_DDR_52] = 52000000,
Jean-Jacques Hiblot78422312017-09-21 16:29:55 +0200169 [UHS_SDR12] = 25000000,
170 [UHS_SDR25] = 50000000,
171 [UHS_SDR50] = 100000000,
Jean-Jacques Hiblot78422312017-09-21 16:29:55 +0200172 [UHS_DDR50] = 50000000,
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +0100173 [UHS_SDR104] = 208000000,
Jean-Jacques Hiblot78422312017-09-21 16:29:55 +0200174 [MMC_HS_200] = 200000000,
Peng Fan46801252018-08-10 14:07:54 +0800175 [MMC_HS_400] = 200000000,
Jean-Jacques Hiblot78422312017-09-21 16:29:55 +0200176 };
177
178 if (mode == MMC_LEGACY)
179 return mmc->legacy_speed;
180 else if (mode >= MMC_MODES_END)
181 return 0;
182 else
183 return freqs[mode];
184}
185
Jean-Jacques Hiblota94fb412017-09-21 16:29:53 +0200186static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
187{
188 mmc->selected_mode = mode;
Jean-Jacques Hiblot78422312017-09-21 16:29:55 +0200189 mmc->tran_speed = mmc_mode2freq(mmc, mode);
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200190 mmc->ddr_mode = mmc_is_mode_ddr(mode);
Masahiro Yamadaf97b1482018-01-28 19:11:42 +0900191 pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
192 mmc->tran_speed / 1000000);
Jean-Jacques Hiblota94fb412017-09-21 16:29:53 +0200193 return 0;
194}
195
Simon Glasseba48f92017-07-29 11:35:31 -0600196#if !CONFIG_IS_ENABLED(DM_MMC)
Simon Glassb23d96e2016-06-12 23:30:20 -0600197int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
198{
199 int ret;
200
201 mmmc_trace_before_send(mmc, cmd);
202 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
203 mmmc_trace_after_send(mmc, cmd, ret);
204
Marek Vasutdccb6082012-03-15 18:41:35 +0000205 return ret;
Andy Flemingad347bb2008-10-30 16:41:01 -0500206}
Simon Glass394dfc02016-06-12 23:30:22 -0600207#endif
Andy Flemingad347bb2008-10-30 16:41:01 -0500208
Paul Burton8d30cc92013-09-09 15:30:26 +0100209int mmc_send_status(struct mmc *mmc, int timeout)
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000210{
211 struct mmc_cmd cmd;
Jan Kloetzke31789322012-02-05 22:29:12 +0000212 int err, retries = 5;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000213
214 cmd.cmdidx = MMC_CMD_SEND_STATUS;
215 cmd.resp_type = MMC_RSP_R1;
Marek Vasutc4427392011-08-10 09:24:48 +0200216 if (!mmc_host_is_spi(mmc))
217 cmd.cmdarg = mmc->rca << 16;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000218
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500219 while (1) {
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000220 err = mmc_send_cmd(mmc, &cmd, NULL);
Jan Kloetzke31789322012-02-05 22:29:12 +0000221 if (!err) {
222 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
223 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
224 MMC_STATE_PRG)
225 break;
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +0200226
227 if (cmd.response[0] & MMC_STATUS_MASK) {
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100228#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +0100229 pr_err("Status Error: 0x%08X\n",
230 cmd.response[0]);
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100231#endif
Jaehoon Chung7825d202016-07-19 16:33:36 +0900232 return -ECOMM;
Jan Kloetzke31789322012-02-05 22:29:12 +0000233 }
234 } else if (--retries < 0)
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000235 return err;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000236
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500237 if (timeout-- <= 0)
238 break;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000239
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500240 udelay(1000);
241 }
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000242
Simon Glassb23d96e2016-06-12 23:30:20 -0600243 mmc_trace_state(mmc, &cmd);
Jongman Heo1be00d92012-06-03 21:32:13 +0000244 if (timeout <= 0) {
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100245#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +0100246 pr_err("Timeout waiting card ready\n");
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100247#endif
Jaehoon Chung7825d202016-07-19 16:33:36 +0900248 return -ETIMEDOUT;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000249 }
250
251 return 0;
252}
253
Paul Burton8d30cc92013-09-09 15:30:26 +0100254int mmc_set_blocklen(struct mmc *mmc, int len)
Andy Flemingad347bb2008-10-30 16:41:01 -0500255{
256 struct mmc_cmd cmd;
Kishon Vijay Abraham I07baaa62017-09-21 16:30:10 +0200257 int err;
Andy Flemingad347bb2008-10-30 16:41:01 -0500258
Andrew Gabbasov9fc2a412014-12-01 06:59:09 -0600259 if (mmc->ddr_mode)
Jaehoon Chung38ce30b2014-05-16 13:59:54 +0900260 return 0;
261
Andy Flemingad347bb2008-10-30 16:41:01 -0500262 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
263 cmd.resp_type = MMC_RSP_R1;
264 cmd.cmdarg = len;
Andy Flemingad347bb2008-10-30 16:41:01 -0500265
Kishon Vijay Abraham I07baaa62017-09-21 16:30:10 +0200266 err = mmc_send_cmd(mmc, &cmd, NULL);
267
268#ifdef CONFIG_MMC_QUIRKS
269 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
270 int retries = 4;
271 /*
272 * It has been seen that SET_BLOCKLEN may fail on the first
273 * attempt, let's try a few more time
274 */
275 do {
276 err = mmc_send_cmd(mmc, &cmd, NULL);
277 if (!err)
278 break;
279 } while (retries--);
280 }
281#endif
282
283 return err;
Andy Flemingad347bb2008-10-30 16:41:01 -0500284}
285
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +0100286#ifdef MMC_SUPPORTS_TUNING
Jean-Jacques Hiblot71264bb2017-09-21 16:30:12 +0200287static const u8 tuning_blk_pattern_4bit[] = {
288 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
289 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
290 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
291 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
292 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
293 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
294 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
295 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
296};
297
298static const u8 tuning_blk_pattern_8bit[] = {
299 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
300 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
301 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
302 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
303 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
304 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
305 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
306 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
307 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
308 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
309 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
310 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
311 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
312 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
313 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
314 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
315};
316
317int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
318{
319 struct mmc_cmd cmd;
320 struct mmc_data data;
321 const u8 *tuning_block_pattern;
322 int size, err;
323
324 if (mmc->bus_width == 8) {
325 tuning_block_pattern = tuning_blk_pattern_8bit;
326 size = sizeof(tuning_blk_pattern_8bit);
327 } else if (mmc->bus_width == 4) {
328 tuning_block_pattern = tuning_blk_pattern_4bit;
329 size = sizeof(tuning_blk_pattern_4bit);
330 } else {
331 return -EINVAL;
332 }
333
334 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
335
336 cmd.cmdidx = opcode;
337 cmd.cmdarg = 0;
338 cmd.resp_type = MMC_RSP_R1;
339
340 data.dest = (void *)data_buf;
341 data.blocks = 1;
342 data.blocksize = size;
343 data.flags = MMC_DATA_READ;
344
345 err = mmc_send_cmd(mmc, &cmd, &data);
346 if (err)
347 return err;
348
349 if (memcmp(data_buf, tuning_block_pattern, size))
350 return -EIO;
351
352 return 0;
353}
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +0100354#endif
Jean-Jacques Hiblot71264bb2017-09-21 16:30:12 +0200355
Sascha Silbe4bdf6fd2013-06-14 13:07:25 +0200356static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
Kim Phillips87ea3892012-10-29 13:34:43 +0000357 lbaint_t blkcnt)
Andy Flemingad347bb2008-10-30 16:41:01 -0500358{
359 struct mmc_cmd cmd;
360 struct mmc_data data;
361
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700362 if (blkcnt > 1)
363 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
364 else
365 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
Andy Flemingad347bb2008-10-30 16:41:01 -0500366
367 if (mmc->high_capacity)
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700368 cmd.cmdarg = start;
Andy Flemingad347bb2008-10-30 16:41:01 -0500369 else
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700370 cmd.cmdarg = start * mmc->read_bl_len;
Andy Flemingad347bb2008-10-30 16:41:01 -0500371
372 cmd.resp_type = MMC_RSP_R1;
Andy Flemingad347bb2008-10-30 16:41:01 -0500373
374 data.dest = dst;
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700375 data.blocks = blkcnt;
Andy Flemingad347bb2008-10-30 16:41:01 -0500376 data.blocksize = mmc->read_bl_len;
377 data.flags = MMC_DATA_READ;
378
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700379 if (mmc_send_cmd(mmc, &cmd, &data))
380 return 0;
Andy Flemingad347bb2008-10-30 16:41:01 -0500381
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700382 if (blkcnt > 1) {
383 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
384 cmd.cmdarg = 0;
385 cmd.resp_type = MMC_RSP_R1b;
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700386 if (mmc_send_cmd(mmc, &cmd, NULL)) {
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100387#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +0100388 pr_err("mmc fail to send stop cmd\n");
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100389#endif
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700390 return 0;
391 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500392 }
393
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700394 return blkcnt;
Andy Flemingad347bb2008-10-30 16:41:01 -0500395}
396
Simon Glass5f4bd8c2017-07-04 13:31:19 -0600397#if CONFIG_IS_ENABLED(BLK)
Simon Glass62e293a2016-06-12 23:30:15 -0600398ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
Simon Glass59bc6f22016-05-01 13:52:41 -0600399#else
Simon Glass62e293a2016-06-12 23:30:15 -0600400ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
401 void *dst)
Simon Glass59bc6f22016-05-01 13:52:41 -0600402#endif
Andy Flemingad347bb2008-10-30 16:41:01 -0500403{
Simon Glass5f4bd8c2017-07-04 13:31:19 -0600404#if CONFIG_IS_ENABLED(BLK)
Simon Glass59bc6f22016-05-01 13:52:41 -0600405 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
406#endif
Simon Glass2f26fff2016-02-29 15:25:51 -0700407 int dev_num = block_dev->devnum;
Stephen Warren1e0f92a2015-12-07 11:38:49 -0700408 int err;
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700409 lbaint_t cur, blocks_todo = blkcnt;
410
411 if (blkcnt == 0)
412 return 0;
Andy Flemingad347bb2008-10-30 16:41:01 -0500413
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700414 struct mmc *mmc = find_mmc_device(dev_num);
Andy Flemingad347bb2008-10-30 16:41:01 -0500415 if (!mmc)
416 return 0;
417
Marek Vasutf537e392016-12-01 02:06:33 +0100418 if (CONFIG_IS_ENABLED(MMC_TINY))
419 err = mmc_switch_part(mmc, block_dev->hwpart);
420 else
421 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
422
Stephen Warren1e0f92a2015-12-07 11:38:49 -0700423 if (err < 0)
424 return 0;
425
Simon Glasse5db1152016-05-01 13:52:35 -0600426 if ((start + blkcnt) > block_dev->lba) {
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100427#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +0100428 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
429 start + blkcnt, block_dev->lba);
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100430#endif
Lei Wene1cc9c82010-09-13 22:07:27 +0800431 return 0;
432 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500433
Simon Glassa4343c42015-06-23 15:38:50 -0600434 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
Masahiro Yamadaf97b1482018-01-28 19:11:42 +0900435 pr_debug("%s: Failed to set blocklen\n", __func__);
Andy Flemingad347bb2008-10-30 16:41:01 -0500436 return 0;
Simon Glassa4343c42015-06-23 15:38:50 -0600437 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500438
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700439 do {
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200440 cur = (blocks_todo > mmc->cfg->b_max) ?
441 mmc->cfg->b_max : blocks_todo;
Simon Glassa4343c42015-06-23 15:38:50 -0600442 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
Masahiro Yamadaf97b1482018-01-28 19:11:42 +0900443 pr_debug("%s: Failed to read blocks\n", __func__);
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700444 return 0;
Simon Glassa4343c42015-06-23 15:38:50 -0600445 }
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700446 blocks_todo -= cur;
447 start += cur;
448 dst += cur * mmc->read_bl_len;
449 } while (blocks_todo > 0);
Andy Flemingad347bb2008-10-30 16:41:01 -0500450
451 return blkcnt;
452}
453
Kim Phillips87ea3892012-10-29 13:34:43 +0000454static int mmc_go_idle(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -0500455{
456 struct mmc_cmd cmd;
457 int err;
458
459 udelay(1000);
460
461 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
462 cmd.cmdarg = 0;
463 cmd.resp_type = MMC_RSP_NONE;
Andy Flemingad347bb2008-10-30 16:41:01 -0500464
465 err = mmc_send_cmd(mmc, &cmd, NULL);
466
467 if (err)
468 return err;
469
470 udelay(2000);
471
472 return 0;
473}
474
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +0100475#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +0200476static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
477{
478 struct mmc_cmd cmd;
479 int err = 0;
480
481 /*
482 * Send CMD11 only if the request is to switch the card to
483 * 1.8V signalling.
484 */
485 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
486 return mmc_set_signal_voltage(mmc, signal_voltage);
487
488 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
489 cmd.cmdarg = 0;
490 cmd.resp_type = MMC_RSP_R1;
491
492 err = mmc_send_cmd(mmc, &cmd, NULL);
493 if (err)
494 return err;
495
496 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
497 return -EIO;
498
499 /*
500 * The card should drive cmd and dat[0:3] low immediately
501 * after the response of cmd11, but wait 100 us to be sure
502 */
503 err = mmc_wait_dat0(mmc, 0, 100);
504 if (err == -ENOSYS)
505 udelay(100);
506 else if (err)
507 return -ETIMEDOUT;
508
509 /*
510 * During a signal voltage level switch, the clock must be gated
511 * for 5 ms according to the SD spec
512 */
Jaehoon Chung239cb2f2018-01-26 19:25:29 +0900513 mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +0200514
515 err = mmc_set_signal_voltage(mmc, signal_voltage);
516 if (err)
517 return err;
518
519 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
520 mdelay(10);
Jaehoon Chung239cb2f2018-01-26 19:25:29 +0900521 mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +0200522
523 /*
524 * Failure to switch is indicated by the card holding
525 * dat[0:3] low. Wait for at least 1 ms according to spec
526 */
527 err = mmc_wait_dat0(mmc, 1, 1000);
528 if (err == -ENOSYS)
529 udelay(1000);
530 else if (err)
531 return -ETIMEDOUT;
532
533 return 0;
534}
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +0100535#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +0200536
537static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
Andy Flemingad347bb2008-10-30 16:41:01 -0500538{
539 int timeout = 1000;
540 int err;
541 struct mmc_cmd cmd;
542
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500543 while (1) {
Andy Flemingad347bb2008-10-30 16:41:01 -0500544 cmd.cmdidx = MMC_CMD_APP_CMD;
545 cmd.resp_type = MMC_RSP_R1;
546 cmd.cmdarg = 0;
Andy Flemingad347bb2008-10-30 16:41:01 -0500547
548 err = mmc_send_cmd(mmc, &cmd, NULL);
549
550 if (err)
551 return err;
552
553 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
554 cmd.resp_type = MMC_RSP_R3;
Stefano Babicf8e9a212010-01-20 18:20:39 +0100555
556 /*
557 * Most cards do not answer if some reserved bits
558 * in the ocr are set. However, Some controller
559 * can set bit 7 (reserved for low voltages), but
560 * how to manage low voltages SD card is not yet
561 * specified.
562 */
Thomas Chou1254c3d2010-12-24 13:12:21 +0000563 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200564 (mmc->cfg->voltages & 0xff8000);
Andy Flemingad347bb2008-10-30 16:41:01 -0500565
566 if (mmc->version == SD_VERSION_2)
567 cmd.cmdarg |= OCR_HCS;
568
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +0200569 if (uhs_en)
570 cmd.cmdarg |= OCR_S18R;
571
Andy Flemingad347bb2008-10-30 16:41:01 -0500572 err = mmc_send_cmd(mmc, &cmd, NULL);
573
574 if (err)
575 return err;
576
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500577 if (cmd.response[0] & OCR_BUSY)
578 break;
Andy Flemingad347bb2008-10-30 16:41:01 -0500579
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500580 if (timeout-- <= 0)
Jaehoon Chung7825d202016-07-19 16:33:36 +0900581 return -EOPNOTSUPP;
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500582
583 udelay(1000);
584 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500585
586 if (mmc->version != SD_VERSION_2)
587 mmc->version = SD_VERSION_1_0;
588
Thomas Chou1254c3d2010-12-24 13:12:21 +0000589 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
590 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
591 cmd.resp_type = MMC_RSP_R3;
592 cmd.cmdarg = 0;
Thomas Chou1254c3d2010-12-24 13:12:21 +0000593
594 err = mmc_send_cmd(mmc, &cmd, NULL);
595
596 if (err)
597 return err;
598 }
599
Rabin Vincentb6eed942009-04-05 13:30:56 +0530600 mmc->ocr = cmd.response[0];
Andy Flemingad347bb2008-10-30 16:41:01 -0500601
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +0100602#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +0200603 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
604 == 0x41000000) {
605 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
606 if (err)
607 return err;
608 }
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +0100609#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +0200610
Andy Flemingad347bb2008-10-30 16:41:01 -0500611 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
612 mmc->rca = 0;
613
614 return 0;
615}
616
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500617static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
Andy Flemingad347bb2008-10-30 16:41:01 -0500618{
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500619 struct mmc_cmd cmd;
Andy Flemingad347bb2008-10-30 16:41:01 -0500620 int err;
621
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500622 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
623 cmd.resp_type = MMC_RSP_R3;
624 cmd.cmdarg = 0;
Rob Herring5fd3edd2015-03-23 17:56:59 -0500625 if (use_arg && !mmc_host_is_spi(mmc))
626 cmd.cmdarg = OCR_HCS |
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200627 (mmc->cfg->voltages &
Andrew Gabbasovec600d12015-03-19 07:44:03 -0500628 (mmc->ocr & OCR_VOLTAGE_MASK)) |
629 (mmc->ocr & OCR_ACCESS_MODE);
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000630
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500631 err = mmc_send_cmd(mmc, &cmd, NULL);
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000632 if (err)
633 return err;
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500634 mmc->ocr = cmd.response[0];
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000635 return 0;
636}
637
Jeroen Hofsteeaedeeaa2014-07-12 21:24:08 +0200638static int mmc_send_op_cond(struct mmc *mmc)
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000639{
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000640 int err, i;
641
Andy Flemingad347bb2008-10-30 16:41:01 -0500642 /* Some cards seem to need this */
643 mmc_go_idle(mmc);
644
Raffaele Recalcati1df837e2011-03-11 02:01:13 +0000645 /* Asking to the card its capabilities */
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000646 for (i = 0; i < 2; i++) {
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500647 err = mmc_send_op_cond_iter(mmc, i != 0);
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000648 if (err)
649 return err;
Wolfgang Denk80f70212011-05-19 22:21:41 +0200650
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000651 /* exit if not busy (flag seems to be inverted) */
Andrew Gabbasovec600d12015-03-19 07:44:03 -0500652 if (mmc->ocr & OCR_BUSY)
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -0500653 break;
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000654 }
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -0500655 mmc->op_cond_pending = 1;
656 return 0;
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000657}
Wolfgang Denk80f70212011-05-19 22:21:41 +0200658
Jeroen Hofsteeaedeeaa2014-07-12 21:24:08 +0200659static int mmc_complete_op_cond(struct mmc *mmc)
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000660{
661 struct mmc_cmd cmd;
662 int timeout = 1000;
Vipul Kumardbad7b42018-05-03 12:20:54 +0530663 ulong start;
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000664 int err;
Wolfgang Denk80f70212011-05-19 22:21:41 +0200665
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000666 mmc->op_cond_pending = 0;
Andrew Gabbasov5a513ca2015-03-19 07:44:05 -0500667 if (!(mmc->ocr & OCR_BUSY)) {
Yangbo Lu9c720612016-08-02 15:33:18 +0800668 /* Some cards seem to need this */
669 mmc_go_idle(mmc);
670
Andrew Gabbasov5a513ca2015-03-19 07:44:05 -0500671 start = get_timer(0);
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500672 while (1) {
Andrew Gabbasov5a513ca2015-03-19 07:44:05 -0500673 err = mmc_send_op_cond_iter(mmc, 1);
674 if (err)
675 return err;
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500676 if (mmc->ocr & OCR_BUSY)
677 break;
Andrew Gabbasov5a513ca2015-03-19 07:44:05 -0500678 if (get_timer(start) > timeout)
Jaehoon Chung7825d202016-07-19 16:33:36 +0900679 return -EOPNOTSUPP;
Andrew Gabbasov5a513ca2015-03-19 07:44:05 -0500680 udelay(100);
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500681 }
Andrew Gabbasov5a513ca2015-03-19 07:44:05 -0500682 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500683
Thomas Chou1254c3d2010-12-24 13:12:21 +0000684 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
685 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
686 cmd.resp_type = MMC_RSP_R3;
687 cmd.cmdarg = 0;
Thomas Chou1254c3d2010-12-24 13:12:21 +0000688
689 err = mmc_send_cmd(mmc, &cmd, NULL);
690
691 if (err)
692 return err;
Andrew Gabbasovec600d12015-03-19 07:44:03 -0500693
694 mmc->ocr = cmd.response[0];
Thomas Chou1254c3d2010-12-24 13:12:21 +0000695 }
696
Andy Flemingad347bb2008-10-30 16:41:01 -0500697 mmc->version = MMC_VERSION_UNKNOWN;
Andy Flemingad347bb2008-10-30 16:41:01 -0500698
699 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
Stephen Warrenf6545f12014-01-30 16:11:12 -0700700 mmc->rca = 1;
Andy Flemingad347bb2008-10-30 16:41:01 -0500701
702 return 0;
703}
704
705
Kim Phillips87ea3892012-10-29 13:34:43 +0000706static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
Andy Flemingad347bb2008-10-30 16:41:01 -0500707{
708 struct mmc_cmd cmd;
709 struct mmc_data data;
710 int err;
711
712 /* Get the Card Status Register */
713 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
714 cmd.resp_type = MMC_RSP_R1;
715 cmd.cmdarg = 0;
Andy Flemingad347bb2008-10-30 16:41:01 -0500716
Yoshihiro Shimodaf6bec732012-06-07 19:09:11 +0000717 data.dest = (char *)ext_csd;
Andy Flemingad347bb2008-10-30 16:41:01 -0500718 data.blocks = 1;
Simon Glassa09c2b72013-04-03 08:54:30 +0000719 data.blocksize = MMC_MAX_BLOCK_LEN;
Andy Flemingad347bb2008-10-30 16:41:01 -0500720 data.flags = MMC_DATA_READ;
721
722 err = mmc_send_cmd(mmc, &cmd, &data);
723
724 return err;
725}
726
Simon Glass84f9df92016-06-12 23:30:18 -0600727int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
Andy Flemingad347bb2008-10-30 16:41:01 -0500728{
729 struct mmc_cmd cmd;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000730 int timeout = 1000;
Maxime Riparde7462aa2016-11-04 16:18:08 +0100731 int retries = 3;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000732 int ret;
Andy Flemingad347bb2008-10-30 16:41:01 -0500733
734 cmd.cmdidx = MMC_CMD_SWITCH;
735 cmd.resp_type = MMC_RSP_R1b;
736 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000737 (index << 16) |
738 (value << 8);
Andy Flemingad347bb2008-10-30 16:41:01 -0500739
Maxime Riparde7462aa2016-11-04 16:18:08 +0100740 while (retries > 0) {
741 ret = mmc_send_cmd(mmc, &cmd, NULL);
742
743 /* Waiting for the ready status */
744 if (!ret) {
745 ret = mmc_send_status(mmc, timeout);
746 return ret;
747 }
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000748
Maxime Riparde7462aa2016-11-04 16:18:08 +0100749 retries--;
750 }
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000751
752 return ret;
753
Andy Flemingad347bb2008-10-30 16:41:01 -0500754}
755
Marek Vasuta318a7a2018-04-15 00:37:11 +0200756#if !CONFIG_IS_ENABLED(MMC_TINY)
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200757static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
Andy Flemingad347bb2008-10-30 16:41:01 -0500758{
Andy Flemingad347bb2008-10-30 16:41:01 -0500759 int err;
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200760 int speed_bits;
761
762 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
763
764 switch (mode) {
765 case MMC_HS:
766 case MMC_HS_52:
767 case MMC_DDR_52:
768 speed_bits = EXT_CSD_TIMING_HS;
Kishon Vijay Abraham I210369f2017-09-21 16:30:06 +0200769 break;
Jean-Jacques Hiblot74c98b22018-01-04 15:23:30 +0100770#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
Kishon Vijay Abraham I210369f2017-09-21 16:30:06 +0200771 case MMC_HS_200:
772 speed_bits = EXT_CSD_TIMING_HS200;
773 break;
Jean-Jacques Hiblot74c98b22018-01-04 15:23:30 +0100774#endif
Peng Fan46801252018-08-10 14:07:54 +0800775#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
776 case MMC_HS_400:
777 speed_bits = EXT_CSD_TIMING_HS400;
778 break;
779#endif
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200780 case MMC_LEGACY:
781 speed_bits = EXT_CSD_TIMING_LEGACY;
782 break;
783 default:
784 return -EINVAL;
785 }
786 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
787 speed_bits);
788 if (err)
789 return err;
790
791 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
792 /* Now check to see that it worked */
793 err = mmc_send_ext_csd(mmc, test_csd);
794 if (err)
795 return err;
796
797 /* No high-speed support */
798 if (!test_csd[EXT_CSD_HS_TIMING])
799 return -ENOTSUPP;
800 }
801
802 return 0;
803}
804
805static int mmc_get_capabilities(struct mmc *mmc)
806{
807 u8 *ext_csd = mmc->ext_csd;
808 char cardtype;
Andy Flemingad347bb2008-10-30 16:41:01 -0500809
Jean-Jacques Hiblot3f2ffc22017-11-30 17:43:56 +0100810 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
Andy Flemingad347bb2008-10-30 16:41:01 -0500811
Thomas Chou1254c3d2010-12-24 13:12:21 +0000812 if (mmc_host_is_spi(mmc))
813 return 0;
814
Andy Flemingad347bb2008-10-30 16:41:01 -0500815 /* Only version 4 supports high-speed */
816 if (mmc->version < MMC_VERSION_4)
817 return 0;
818
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200819 if (!ext_csd) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +0100820 pr_err("No ext_csd found!\n"); /* this should enver happen */
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200821 return -ENOTSUPP;
822 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500823
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200824 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
Andy Flemingad347bb2008-10-30 16:41:01 -0500825
Peng Fan46801252018-08-10 14:07:54 +0800826 cardtype = ext_csd[EXT_CSD_CARD_TYPE];
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +0200827 mmc->cardtype = cardtype;
Andy Flemingad347bb2008-10-30 16:41:01 -0500828
Jean-Jacques Hiblot74c98b22018-01-04 15:23:30 +0100829#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
Kishon Vijay Abraham I210369f2017-09-21 16:30:06 +0200830 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
831 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
832 mmc->card_caps |= MMC_MODE_HS200;
833 }
Jean-Jacques Hiblot74c98b22018-01-04 15:23:30 +0100834#endif
Peng Fan46801252018-08-10 14:07:54 +0800835#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
836 if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
837 EXT_CSD_CARD_TYPE_HS400_1_8V)) {
838 mmc->card_caps |= MMC_MODE_HS400;
839 }
840#endif
Jaehoon Chung38ce30b2014-05-16 13:59:54 +0900841 if (cardtype & EXT_CSD_CARD_TYPE_52) {
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200842 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
Jaehoon Chung38ce30b2014-05-16 13:59:54 +0900843 mmc->card_caps |= MMC_MODE_DDR_52MHz;
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200844 mmc->card_caps |= MMC_MODE_HS_52MHz;
Jaehoon Chung38ce30b2014-05-16 13:59:54 +0900845 }
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +0200846 if (cardtype & EXT_CSD_CARD_TYPE_26)
847 mmc->card_caps |= MMC_MODE_HS;
Andy Flemingad347bb2008-10-30 16:41:01 -0500848
849 return 0;
850}
Marek Vasuta318a7a2018-04-15 00:37:11 +0200851#endif
Andy Flemingad347bb2008-10-30 16:41:01 -0500852
Stephen Warrene315ae82013-06-11 15:14:01 -0600853static int mmc_set_capacity(struct mmc *mmc, int part_num)
854{
855 switch (part_num) {
856 case 0:
857 mmc->capacity = mmc->capacity_user;
858 break;
859 case 1:
860 case 2:
861 mmc->capacity = mmc->capacity_boot;
862 break;
863 case 3:
864 mmc->capacity = mmc->capacity_rpmb;
865 break;
866 case 4:
867 case 5:
868 case 6:
869 case 7:
870 mmc->capacity = mmc->capacity_gp[part_num - 4];
871 break;
872 default:
873 return -1;
874 }
875
Simon Glasse5db1152016-05-01 13:52:35 -0600876 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
Stephen Warrene315ae82013-06-11 15:14:01 -0600877
878 return 0;
879}
880
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +0100881#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
Jean-Jacques Hiblot3d30972b2017-09-21 16:30:09 +0200882static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
883{
884 int forbidden = 0;
885 bool change = false;
886
887 if (part_num & PART_ACCESS_MASK)
888 forbidden = MMC_CAP(MMC_HS_200);
889
890 if (MMC_CAP(mmc->selected_mode) & forbidden) {
Masahiro Yamadaf97b1482018-01-28 19:11:42 +0900891 pr_debug("selected mode (%s) is forbidden for part %d\n",
892 mmc_mode_name(mmc->selected_mode), part_num);
Jean-Jacques Hiblot3d30972b2017-09-21 16:30:09 +0200893 change = true;
894 } else if (mmc->selected_mode != mmc->best_mode) {
Masahiro Yamadaf97b1482018-01-28 19:11:42 +0900895 pr_debug("selected mode is not optimal\n");
Jean-Jacques Hiblot3d30972b2017-09-21 16:30:09 +0200896 change = true;
897 }
898
899 if (change)
900 return mmc_select_mode_and_width(mmc,
901 mmc->card_caps & ~forbidden);
902
903 return 0;
904}
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +0100905#else
906static inline int mmc_boot_part_access_chk(struct mmc *mmc,
907 unsigned int part_num)
908{
909 return 0;
910}
911#endif
Jean-Jacques Hiblot3d30972b2017-09-21 16:30:09 +0200912
Simon Glass62e293a2016-06-12 23:30:15 -0600913int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
Lei Wen31b99802011-05-02 16:26:26 +0000914{
Stephen Warrene315ae82013-06-11 15:14:01 -0600915 int ret;
Lei Wen31b99802011-05-02 16:26:26 +0000916
Jean-Jacques Hiblot3d30972b2017-09-21 16:30:09 +0200917 ret = mmc_boot_part_access_chk(mmc, part_num);
918 if (ret)
919 return ret;
920
Stephen Warrene315ae82013-06-11 15:14:01 -0600921 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
922 (mmc->part_config & ~PART_ACCESS_MASK)
923 | (part_num & PART_ACCESS_MASK));
Peter Bigot45fde892014-09-02 18:31:23 -0500924
925 /*
926 * Set the capacity if the switch succeeded or was intended
927 * to return to representing the raw device.
928 */
Stephen Warren1e0f92a2015-12-07 11:38:49 -0700929 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
Peter Bigot45fde892014-09-02 18:31:23 -0500930 ret = mmc_set_capacity(mmc, part_num);
Simon Glass984db5d2016-05-01 13:52:37 -0600931 mmc_get_blk_desc(mmc)->hwpart = part_num;
Stephen Warren1e0f92a2015-12-07 11:38:49 -0700932 }
Stephen Warrene315ae82013-06-11 15:14:01 -0600933
Peter Bigot45fde892014-09-02 18:31:23 -0500934 return ret;
Lei Wen31b99802011-05-02 16:26:26 +0000935}
936
Jean-Jacques Hiblot1d7769a2017-11-30 17:44:02 +0100937#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +0100938int mmc_hwpart_config(struct mmc *mmc,
939 const struct mmc_hwpart_conf *conf,
940 enum mmc_hwpart_conf_mode mode)
941{
942 u8 part_attrs = 0;
943 u32 enh_size_mult;
944 u32 enh_start_addr;
945 u32 gp_size_mult[4];
946 u32 max_enh_size_mult;
947 u32 tot_enh_size_mult = 0;
Diego Santa Cruz80200272014-12-23 10:50:31 +0100948 u8 wr_rel_set;
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +0100949 int i, pidx, err;
950 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
951
952 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
953 return -EINVAL;
954
955 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +0100956 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +0100957 return -EMEDIUMTYPE;
958 }
959
960 if (!(mmc->part_support & PART_SUPPORT)) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +0100961 pr_err("Card does not support partitioning\n");
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +0100962 return -EMEDIUMTYPE;
963 }
964
965 if (!mmc->hc_wp_grp_size) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +0100966 pr_err("Card does not define HC WP group size\n");
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +0100967 return -EMEDIUMTYPE;
968 }
969
970 /* check partition alignment and total enhanced size */
971 if (conf->user.enh_size) {
972 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
973 conf->user.enh_start % mmc->hc_wp_grp_size) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +0100974 pr_err("User data enhanced area not HC WP group "
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +0100975 "size aligned\n");
976 return -EINVAL;
977 }
978 part_attrs |= EXT_CSD_ENH_USR;
979 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
980 if (mmc->high_capacity) {
981 enh_start_addr = conf->user.enh_start;
982 } else {
983 enh_start_addr = (conf->user.enh_start << 9);
984 }
985 } else {
986 enh_size_mult = 0;
987 enh_start_addr = 0;
988 }
989 tot_enh_size_mult += enh_size_mult;
990
991 for (pidx = 0; pidx < 4; pidx++) {
992 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +0100993 pr_err("GP%i partition not HC WP group size "
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +0100994 "aligned\n", pidx+1);
995 return -EINVAL;
996 }
997 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
998 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
999 part_attrs |= EXT_CSD_ENH_GP(pidx);
1000 tot_enh_size_mult += gp_size_mult[pidx];
1001 }
1002 }
1003
1004 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01001005 pr_err("Card does not support enhanced attribute\n");
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001006 return -EMEDIUMTYPE;
1007 }
1008
1009 err = mmc_send_ext_csd(mmc, ext_csd);
1010 if (err)
1011 return err;
1012
1013 max_enh_size_mult =
1014 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1015 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1016 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1017 if (tot_enh_size_mult > max_enh_size_mult) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01001018 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001019 tot_enh_size_mult, max_enh_size_mult);
1020 return -EMEDIUMTYPE;
1021 }
1022
Diego Santa Cruz80200272014-12-23 10:50:31 +01001023 /* The default value of EXT_CSD_WR_REL_SET is device
1024 * dependent, the values can only be changed if the
1025 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1026 * changed only once and before partitioning is completed. */
1027 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1028 if (conf->user.wr_rel_change) {
1029 if (conf->user.wr_rel_set)
1030 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1031 else
1032 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1033 }
1034 for (pidx = 0; pidx < 4; pidx++) {
1035 if (conf->gp_part[pidx].wr_rel_change) {
1036 if (conf->gp_part[pidx].wr_rel_set)
1037 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1038 else
1039 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1040 }
1041 }
1042
1043 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1044 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1045 puts("Card does not support host controlled partition write "
1046 "reliability settings\n");
1047 return -EMEDIUMTYPE;
1048 }
1049
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001050 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1051 EXT_CSD_PARTITION_SETTING_COMPLETED) {
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01001052 pr_err("Card already partitioned\n");
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001053 return -EPERM;
1054 }
1055
1056 if (mode == MMC_HWPART_CONF_CHECK)
1057 return 0;
1058
1059 /* Partitioning requires high-capacity size definitions */
1060 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1061 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1062 EXT_CSD_ERASE_GROUP_DEF, 1);
1063
1064 if (err)
1065 return err;
1066
1067 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1068
1069 /* update erase group size to be high-capacity */
1070 mmc->erase_grp_size =
1071 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1072
1073 }
1074
1075 /* all OK, write the configuration */
1076 for (i = 0; i < 4; i++) {
1077 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1078 EXT_CSD_ENH_START_ADDR+i,
1079 (enh_start_addr >> (i*8)) & 0xFF);
1080 if (err)
1081 return err;
1082 }
1083 for (i = 0; i < 3; i++) {
1084 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1085 EXT_CSD_ENH_SIZE_MULT+i,
1086 (enh_size_mult >> (i*8)) & 0xFF);
1087 if (err)
1088 return err;
1089 }
1090 for (pidx = 0; pidx < 4; pidx++) {
1091 for (i = 0; i < 3; i++) {
1092 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1093 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1094 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1095 if (err)
1096 return err;
1097 }
1098 }
1099 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1100 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1101 if (err)
1102 return err;
1103
1104 if (mode == MMC_HWPART_CONF_SET)
1105 return 0;
1106
Diego Santa Cruz80200272014-12-23 10:50:31 +01001107 /* The WR_REL_SET is a write-once register but shall be
1108 * written before setting PART_SETTING_COMPLETED. As it is
1109 * write-once we can only write it when completing the
1110 * partitioning. */
1111 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1112 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1113 EXT_CSD_WR_REL_SET, wr_rel_set);
1114 if (err)
1115 return err;
1116 }
1117
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001118 /* Setting PART_SETTING_COMPLETED confirms the partition
1119 * configuration but it only becomes effective after power
1120 * cycle, so we do not adjust the partition related settings
1121 * in the mmc struct. */
1122
1123 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1124 EXT_CSD_PARTITION_SETTING,
1125 EXT_CSD_PARTITION_SETTING_COMPLETED);
1126 if (err)
1127 return err;
1128
1129 return 0;
1130}
Jean-Jacques Hiblot1d7769a2017-11-30 17:44:02 +01001131#endif
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +01001132
Simon Glasseba48f92017-07-29 11:35:31 -06001133#if !CONFIG_IS_ENABLED(DM_MMC)
Thierry Redingb9c8b772012-01-02 01:15:37 +00001134int mmc_getcd(struct mmc *mmc)
1135{
1136 int cd;
1137
1138 cd = board_mmc_getcd(mmc);
1139
Peter Korsgaardf7b15102013-03-21 04:00:03 +00001140 if (cd < 0) {
Pantelis Antoniou2c850462014-03-11 19:34:20 +02001141 if (mmc->cfg->ops->getcd)
1142 cd = mmc->cfg->ops->getcd(mmc);
Peter Korsgaardf7b15102013-03-21 04:00:03 +00001143 else
1144 cd = 1;
1145 }
Thierry Redingb9c8b772012-01-02 01:15:37 +00001146
1147 return cd;
1148}
Simon Glass394dfc02016-06-12 23:30:22 -06001149#endif
Thierry Redingb9c8b772012-01-02 01:15:37 +00001150
Marek Vasuta318a7a2018-04-15 00:37:11 +02001151#if !CONFIG_IS_ENABLED(MMC_TINY)
Kim Phillips87ea3892012-10-29 13:34:43 +00001152static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
Andy Flemingad347bb2008-10-30 16:41:01 -05001153{
1154 struct mmc_cmd cmd;
1155 struct mmc_data data;
1156
1157 /* Switch the frequency */
1158 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1159 cmd.resp_type = MMC_RSP_R1;
1160 cmd.cmdarg = (mode << 31) | 0xffffff;
1161 cmd.cmdarg &= ~(0xf << (group * 4));
1162 cmd.cmdarg |= value << (group * 4);
Andy Flemingad347bb2008-10-30 16:41:01 -05001163
1164 data.dest = (char *)resp;
1165 data.blocksize = 64;
1166 data.blocks = 1;
1167 data.flags = MMC_DATA_READ;
1168
1169 return mmc_send_cmd(mmc, &cmd, &data);
1170}
1171
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001172static int sd_get_capabilities(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -05001173{
1174 int err;
1175 struct mmc_cmd cmd;
Suniel Mahesh2f423da2017-10-05 11:32:00 +05301176 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1177 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
Andy Flemingad347bb2008-10-30 16:41:01 -05001178 struct mmc_data data;
1179 int timeout;
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001180#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001181 u32 sd3_bus_mode;
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001182#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05001183
Jean-Jacques Hiblot3f2ffc22017-11-30 17:43:56 +01001184 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
Andy Flemingad347bb2008-10-30 16:41:01 -05001185
Thomas Chou1254c3d2010-12-24 13:12:21 +00001186 if (mmc_host_is_spi(mmc))
1187 return 0;
1188
Andy Flemingad347bb2008-10-30 16:41:01 -05001189 /* Read the SCR to find out if this card supports higher speeds */
1190 cmd.cmdidx = MMC_CMD_APP_CMD;
1191 cmd.resp_type = MMC_RSP_R1;
1192 cmd.cmdarg = mmc->rca << 16;
Andy Flemingad347bb2008-10-30 16:41:01 -05001193
1194 err = mmc_send_cmd(mmc, &cmd, NULL);
1195
1196 if (err)
1197 return err;
1198
1199 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1200 cmd.resp_type = MMC_RSP_R1;
1201 cmd.cmdarg = 0;
Andy Flemingad347bb2008-10-30 16:41:01 -05001202
1203 timeout = 3;
1204
1205retry_scr:
Anton staaf9b00f0d2011-10-03 13:54:59 +00001206 data.dest = (char *)scr;
Andy Flemingad347bb2008-10-30 16:41:01 -05001207 data.blocksize = 8;
1208 data.blocks = 1;
1209 data.flags = MMC_DATA_READ;
1210
1211 err = mmc_send_cmd(mmc, &cmd, &data);
1212
1213 if (err) {
1214 if (timeout--)
1215 goto retry_scr;
1216
1217 return err;
1218 }
1219
Yauhen Kharuzhy6e8edf42009-05-07 00:43:30 +03001220 mmc->scr[0] = __be32_to_cpu(scr[0]);
1221 mmc->scr[1] = __be32_to_cpu(scr[1]);
Andy Flemingad347bb2008-10-30 16:41:01 -05001222
1223 switch ((mmc->scr[0] >> 24) & 0xf) {
Bin Meng4a4ef872016-03-17 21:53:13 -07001224 case 0:
1225 mmc->version = SD_VERSION_1_0;
1226 break;
1227 case 1:
1228 mmc->version = SD_VERSION_1_10;
1229 break;
1230 case 2:
1231 mmc->version = SD_VERSION_2;
1232 if ((mmc->scr[0] >> 15) & 0x1)
1233 mmc->version = SD_VERSION_3;
1234 break;
1235 default:
1236 mmc->version = SD_VERSION_1_0;
1237 break;
Andy Flemingad347bb2008-10-30 16:41:01 -05001238 }
1239
Alagu Sankar24bb5ab2010-05-12 15:08:24 +05301240 if (mmc->scr[0] & SD_DATA_4BIT)
1241 mmc->card_caps |= MMC_MODE_4BIT;
1242
Andy Flemingad347bb2008-10-30 16:41:01 -05001243 /* Version 1.0 doesn't support switching */
1244 if (mmc->version == SD_VERSION_1_0)
1245 return 0;
1246
1247 timeout = 4;
1248 while (timeout--) {
1249 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
Anton staaf9b00f0d2011-10-03 13:54:59 +00001250 (u8 *)switch_status);
Andy Flemingad347bb2008-10-30 16:41:01 -05001251
1252 if (err)
1253 return err;
1254
1255 /* The high-speed function is busy. Try again */
Yauhen Kharuzhy6e8edf42009-05-07 00:43:30 +03001256 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
Andy Flemingad347bb2008-10-30 16:41:01 -05001257 break;
1258 }
1259
Andy Flemingad347bb2008-10-30 16:41:01 -05001260 /* If high-speed isn't supported, we return */
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001261 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1262 mmc->card_caps |= MMC_CAP(SD_HS);
Andy Flemingad347bb2008-10-30 16:41:01 -05001263
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001264#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001265 /* Version before 3.0 don't support UHS modes */
1266 if (mmc->version < SD_VERSION_3)
1267 return 0;
1268
1269 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1270 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1271 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1272 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1273 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1274 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1275 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1276 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1277 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1278 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1279 mmc->card_caps |= MMC_CAP(UHS_DDR50);
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001280#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001281
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001282 return 0;
1283}
1284
1285static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1286{
1287 int err;
1288
1289 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001290 int speed;
Macpaul Lin24e92ec2011-11-28 16:31:09 +00001291
Marek Vasut4105e972018-11-18 03:25:08 +01001292 /* SD version 1.00 and 1.01 does not support CMD 6 */
1293 if (mmc->version == SD_VERSION_1_0)
1294 return 0;
1295
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001296 switch (mode) {
1297 case SD_LEGACY:
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001298 speed = UHS_SDR12_BUS_SPEED;
1299 break;
1300 case SD_HS:
Jean-Jacques Hiblot74c98b22018-01-04 15:23:30 +01001301 speed = HIGH_SPEED_BUS_SPEED;
1302 break;
1303#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1304 case UHS_SDR12:
1305 speed = UHS_SDR12_BUS_SPEED;
1306 break;
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001307 case UHS_SDR25:
1308 speed = UHS_SDR25_BUS_SPEED;
1309 break;
1310 case UHS_SDR50:
1311 speed = UHS_SDR50_BUS_SPEED;
1312 break;
1313 case UHS_DDR50:
1314 speed = UHS_DDR50_BUS_SPEED;
1315 break;
1316 case UHS_SDR104:
1317 speed = UHS_SDR104_BUS_SPEED;
1318 break;
Jean-Jacques Hiblot74c98b22018-01-04 15:23:30 +01001319#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001320 default:
1321 return -EINVAL;
1322 }
1323
1324 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001325 if (err)
1326 return err;
1327
Jean-Jacques Hiblote7f664e2018-02-09 12:09:27 +01001328 if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001329 return -ENOTSUPP;
1330
1331 return 0;
1332}
Andy Flemingad347bb2008-10-30 16:41:01 -05001333
Marek Vasut8ff55fb2018-04-15 00:36:45 +02001334static int sd_select_bus_width(struct mmc *mmc, int w)
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001335{
1336 int err;
1337 struct mmc_cmd cmd;
1338
1339 if ((w != 4) && (w != 1))
1340 return -EINVAL;
1341
1342 cmd.cmdidx = MMC_CMD_APP_CMD;
1343 cmd.resp_type = MMC_RSP_R1;
1344 cmd.cmdarg = mmc->rca << 16;
1345
1346 err = mmc_send_cmd(mmc, &cmd, NULL);
Andy Flemingad347bb2008-10-30 16:41:01 -05001347 if (err)
1348 return err;
1349
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001350 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1351 cmd.resp_type = MMC_RSP_R1;
1352 if (w == 4)
1353 cmd.cmdarg = 2;
1354 else if (w == 1)
1355 cmd.cmdarg = 0;
1356 err = mmc_send_cmd(mmc, &cmd, NULL);
1357 if (err)
1358 return err;
Andy Flemingad347bb2008-10-30 16:41:01 -05001359
1360 return 0;
1361}
Marek Vasuta318a7a2018-04-15 00:37:11 +02001362#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05001363
Jean-Jacques Hiblotcb534f02018-01-04 15:23:33 +01001364#if CONFIG_IS_ENABLED(MMC_WRITE)
Peng Fanb3fcf1e2016-09-01 11:13:38 +08001365static int sd_read_ssr(struct mmc *mmc)
1366{
Jean-Jacques Hiblotcb534f02018-01-04 15:23:33 +01001367 static const unsigned int sd_au_size[] = {
1368 0, SZ_16K / 512, SZ_32K / 512,
1369 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
1370 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
1371 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
1372 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1373 SZ_64M / 512,
1374 };
Peng Fanb3fcf1e2016-09-01 11:13:38 +08001375 int err, i;
1376 struct mmc_cmd cmd;
1377 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1378 struct mmc_data data;
1379 int timeout = 3;
1380 unsigned int au, eo, et, es;
1381
1382 cmd.cmdidx = MMC_CMD_APP_CMD;
1383 cmd.resp_type = MMC_RSP_R1;
1384 cmd.cmdarg = mmc->rca << 16;
1385
1386 err = mmc_send_cmd(mmc, &cmd, NULL);
1387 if (err)
1388 return err;
1389
1390 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1391 cmd.resp_type = MMC_RSP_R1;
1392 cmd.cmdarg = 0;
1393
1394retry_ssr:
1395 data.dest = (char *)ssr;
1396 data.blocksize = 64;
1397 data.blocks = 1;
1398 data.flags = MMC_DATA_READ;
1399
1400 err = mmc_send_cmd(mmc, &cmd, &data);
1401 if (err) {
1402 if (timeout--)
1403 goto retry_ssr;
1404
1405 return err;
1406 }
1407
1408 for (i = 0; i < 16; i++)
1409 ssr[i] = be32_to_cpu(ssr[i]);
1410
1411 au = (ssr[2] >> 12) & 0xF;
1412 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1413 mmc->ssr.au = sd_au_size[au];
1414 es = (ssr[3] >> 24) & 0xFF;
1415 es |= (ssr[2] & 0xFF) << 8;
1416 et = (ssr[3] >> 18) & 0x3F;
1417 if (es && et) {
1418 eo = (ssr[3] >> 16) & 0x3;
1419 mmc->ssr.erase_timeout = (et * 1000) / es;
1420 mmc->ssr.erase_offset = eo * 1000;
1421 }
1422 } else {
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001423 pr_debug("Invalid Allocation Unit Size.\n");
Peng Fanb3fcf1e2016-09-01 11:13:38 +08001424 }
1425
1426 return 0;
1427}
Jean-Jacques Hiblotcb534f02018-01-04 15:23:33 +01001428#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05001429/* frequency bases */
1430/* divided by 10 to be nice to platforms without floating point */
Mike Frysingerb588caf2010-10-20 01:15:53 +00001431static const int fbase[] = {
Andy Flemingad347bb2008-10-30 16:41:01 -05001432 10000,
1433 100000,
1434 1000000,
1435 10000000,
1436};
1437
1438/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1439 * to platforms without floating point.
1440 */
Simon Glass03317cc2016-05-14 14:02:57 -06001441static const u8 multipliers[] = {
Andy Flemingad347bb2008-10-30 16:41:01 -05001442 0, /* reserved */
1443 10,
1444 12,
1445 13,
1446 15,
1447 20,
1448 25,
1449 30,
1450 35,
1451 40,
1452 45,
1453 50,
1454 55,
1455 60,
1456 70,
1457 80,
1458};
1459
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001460static inline int bus_width(uint cap)
1461{
1462 if (cap == MMC_MODE_8BIT)
1463 return 8;
1464 if (cap == MMC_MODE_4BIT)
1465 return 4;
1466 if (cap == MMC_MODE_1BIT)
1467 return 1;
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01001468 pr_warn("invalid bus witdh capability 0x%x\n", cap);
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001469 return 0;
1470}
1471
Simon Glasseba48f92017-07-29 11:35:31 -06001472#if !CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001473#ifdef MMC_SUPPORTS_TUNING
Kishon Vijay Abraham Iae7174f2017-09-21 16:30:05 +02001474static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1475{
1476 return -ENOTSUPP;
1477}
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001478#endif
Kishon Vijay Abraham Iae7174f2017-09-21 16:30:05 +02001479
Jean-Jacques Hiblot5f23d872017-09-21 16:30:01 +02001480static void mmc_send_init_stream(struct mmc *mmc)
1481{
1482}
1483
Kishon Vijay Abraham Ie178c112017-09-21 16:29:59 +02001484static int mmc_set_ios(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -05001485{
Kishon Vijay Abraham Ie178c112017-09-21 16:29:59 +02001486 int ret = 0;
1487
Pantelis Antoniou2c850462014-03-11 19:34:20 +02001488 if (mmc->cfg->ops->set_ios)
Kishon Vijay Abraham Ie178c112017-09-21 16:29:59 +02001489 ret = mmc->cfg->ops->set_ios(mmc);
1490
1491 return ret;
Andy Flemingad347bb2008-10-30 16:41:01 -05001492}
Simon Glass394dfc02016-06-12 23:30:22 -06001493#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05001494
Kishon Vijay Abraham Id6246bf2017-09-21 16:30:03 +02001495int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
Andy Flemingad347bb2008-10-30 16:41:01 -05001496{
Jaehoon Chungab4d4052018-01-23 14:04:30 +09001497 if (!disable) {
Jaehoon Chung8a933292018-01-17 19:36:58 +09001498 if (clock > mmc->cfg->f_max)
1499 clock = mmc->cfg->f_max;
Andy Flemingad347bb2008-10-30 16:41:01 -05001500
Jaehoon Chung8a933292018-01-17 19:36:58 +09001501 if (clock < mmc->cfg->f_min)
1502 clock = mmc->cfg->f_min;
1503 }
Andy Flemingad347bb2008-10-30 16:41:01 -05001504
1505 mmc->clock = clock;
Kishon Vijay Abraham Id6246bf2017-09-21 16:30:03 +02001506 mmc->clk_disable = disable;
Andy Flemingad347bb2008-10-30 16:41:01 -05001507
Jaehoon Chungc8477d62018-01-26 19:25:30 +09001508 debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
1509
Kishon Vijay Abraham Ie178c112017-09-21 16:29:59 +02001510 return mmc_set_ios(mmc);
Andy Flemingad347bb2008-10-30 16:41:01 -05001511}
1512
Kishon Vijay Abraham Ie178c112017-09-21 16:29:59 +02001513static int mmc_set_bus_width(struct mmc *mmc, uint width)
Andy Flemingad347bb2008-10-30 16:41:01 -05001514{
1515 mmc->bus_width = width;
1516
Kishon Vijay Abraham Ie178c112017-09-21 16:29:59 +02001517 return mmc_set_ios(mmc);
Andy Flemingad347bb2008-10-30 16:41:01 -05001518}
1519
Jean-Jacques Hiblot00de5042017-09-21 16:29:54 +02001520#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1521/*
1522 * helper function to display the capabilities in a human
1523 * friendly manner. The capabilities include bus width and
1524 * supported modes.
1525 */
1526void mmc_dump_capabilities(const char *text, uint caps)
1527{
1528 enum bus_mode mode;
1529
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001530 pr_debug("%s: widths [", text);
Jean-Jacques Hiblot00de5042017-09-21 16:29:54 +02001531 if (caps & MMC_MODE_8BIT)
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001532 pr_debug("8, ");
Jean-Jacques Hiblot00de5042017-09-21 16:29:54 +02001533 if (caps & MMC_MODE_4BIT)
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001534 pr_debug("4, ");
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001535 if (caps & MMC_MODE_1BIT)
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001536 pr_debug("1, ");
1537 pr_debug("\b\b] modes [");
Jean-Jacques Hiblot00de5042017-09-21 16:29:54 +02001538 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1539 if (MMC_CAP(mode) & caps)
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001540 pr_debug("%s, ", mmc_mode_name(mode));
1541 pr_debug("\b\b]\n");
Jean-Jacques Hiblot00de5042017-09-21 16:29:54 +02001542}
1543#endif
1544
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001545struct mode_width_tuning {
1546 enum bus_mode mode;
1547 uint widths;
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001548#ifdef MMC_SUPPORTS_TUNING
Kishon Vijay Abraham I210369f2017-09-21 16:30:06 +02001549 uint tuning;
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001550#endif
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001551};
1552
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001553#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001554int mmc_voltage_to_mv(enum mmc_voltage voltage)
1555{
1556 switch (voltage) {
1557 case MMC_SIGNAL_VOLTAGE_000: return 0;
1558 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1559 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1560 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1561 }
1562 return -EINVAL;
1563}
1564
Kishon Vijay Abraham I4afb12b2017-09-21 16:30:00 +02001565static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1566{
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001567 int err;
1568
1569 if (mmc->signal_voltage == signal_voltage)
1570 return 0;
1571
Kishon Vijay Abraham I4afb12b2017-09-21 16:30:00 +02001572 mmc->signal_voltage = signal_voltage;
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001573 err = mmc_set_ios(mmc);
1574 if (err)
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001575 pr_debug("unable to set voltage (err %d)\n", err);
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001576
1577 return err;
Kishon Vijay Abraham I4afb12b2017-09-21 16:30:00 +02001578}
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001579#else
1580static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1581{
1582 return 0;
1583}
1584#endif
Kishon Vijay Abraham I4afb12b2017-09-21 16:30:00 +02001585
Marek Vasuta318a7a2018-04-15 00:37:11 +02001586#if !CONFIG_IS_ENABLED(MMC_TINY)
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001587static const struct mode_width_tuning sd_modes_by_pref[] = {
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001588#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1589#ifdef MMC_SUPPORTS_TUNING
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001590 {
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001591 .mode = UHS_SDR104,
1592 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1593 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1594 },
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001595#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001596 {
1597 .mode = UHS_SDR50,
1598 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1599 },
1600 {
1601 .mode = UHS_DDR50,
1602 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1603 },
1604 {
1605 .mode = UHS_SDR25,
1606 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1607 },
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001608#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001609 {
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001610 .mode = SD_HS,
1611 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1612 },
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001613#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001614 {
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001615 .mode = UHS_SDR12,
1616 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1617 },
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001618#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001619 {
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001620 .mode = SD_LEGACY,
1621 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1622 }
1623};
1624
1625#define for_each_sd_mode_by_pref(caps, mwt) \
1626 for (mwt = sd_modes_by_pref;\
1627 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1628 mwt++) \
1629 if (caps & MMC_CAP(mwt->mode))
1630
Jean-Jacques Hiblot3d30972b2017-09-21 16:30:09 +02001631static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001632{
1633 int err;
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001634 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1635 const struct mode_width_tuning *mwt;
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001636#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001637 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001638#else
1639 bool uhs_en = false;
1640#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001641 uint caps;
1642
Jean-Jacques Hiblot93c31d12017-11-30 17:43:54 +01001643#ifdef DEBUG
1644 mmc_dump_capabilities("sd card", card_caps);
Jean-Jacques Hiblotd7e5e032017-11-30 17:43:57 +01001645 mmc_dump_capabilities("host", mmc->host_caps);
Jean-Jacques Hiblot93c31d12017-11-30 17:43:54 +01001646#endif
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001647
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001648 /* Restrict card's capabilities by what the host can do */
Jean-Jacques Hiblotd7e5e032017-11-30 17:43:57 +01001649 caps = card_caps & mmc->host_caps;
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001650
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001651 if (!uhs_en)
1652 caps &= ~UHS_CAPS;
1653
1654 for_each_sd_mode_by_pref(caps, mwt) {
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001655 uint *w;
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001656
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001657 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001658 if (*w & caps & mwt->widths) {
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001659 pr_debug("trying mode %s width %d (at %d MHz)\n",
1660 mmc_mode_name(mwt->mode),
1661 bus_width(*w),
1662 mmc_mode2freq(mmc, mwt->mode) / 1000000);
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001663
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001664 /* configure the bus width (card + host) */
1665 err = sd_select_bus_width(mmc, bus_width(*w));
1666 if (err)
1667 goto error;
1668 mmc_set_bus_width(mmc, bus_width(*w));
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001669
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001670 /* configure the bus mode (card) */
1671 err = sd_set_card_speed(mmc, mwt->mode);
1672 if (err)
1673 goto error;
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001674
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001675 /* configure the bus mode (host) */
1676 mmc_select_mode(mmc, mwt->mode);
Jaehoon Chung239cb2f2018-01-26 19:25:29 +09001677 mmc_set_clock(mmc, mmc->tran_speed,
1678 MMC_CLK_ENABLE);
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001679
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001680#ifdef MMC_SUPPORTS_TUNING
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001681 /* execute tuning if needed */
1682 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1683 err = mmc_execute_tuning(mmc,
1684 mwt->tuning);
1685 if (err) {
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001686 pr_debug("tuning failed\n");
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001687 goto error;
1688 }
1689 }
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001690#endif
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02001691
Jean-Jacques Hiblotcb534f02018-01-04 15:23:33 +01001692#if CONFIG_IS_ENABLED(MMC_WRITE)
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001693 err = sd_read_ssr(mmc);
Peng Fan2d2fe8e2018-03-05 16:20:40 +08001694 if (err)
Jean-Jacques Hiblotcb534f02018-01-04 15:23:33 +01001695 pr_warn("unable to read ssr\n");
1696#endif
1697 if (!err)
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001698 return 0;
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001699
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001700error:
1701 /* revert to a safer bus speed */
1702 mmc_select_mode(mmc, SD_LEGACY);
Jaehoon Chung239cb2f2018-01-26 19:25:29 +09001703 mmc_set_clock(mmc, mmc->tran_speed,
1704 MMC_CLK_ENABLE);
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001705 }
1706 }
1707 }
1708
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001709 pr_err("unable to select a mode\n");
Jean-Jacques Hiblot5b1a4d92017-09-21 16:29:57 +02001710 return -ENOTSUPP;
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001711}
1712
Jean-Jacques Hiblot933d1262017-09-21 16:29:52 +02001713/*
1714 * read the compare the part of ext csd that is constant.
1715 * This can be used to check that the transfer is working
1716 * as expected.
1717 */
1718static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001719{
Jean-Jacques Hiblot933d1262017-09-21 16:29:52 +02001720 int err;
Jean-Jacques Hibloted9506b2017-09-21 16:29:51 +02001721 const u8 *ext_csd = mmc->ext_csd;
Jean-Jacques Hiblot933d1262017-09-21 16:29:52 +02001722 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1723
Jean-Jacques Hiblot7ab1b622017-11-30 17:43:58 +01001724 if (mmc->version < MMC_VERSION_4)
1725 return 0;
1726
Jean-Jacques Hiblot933d1262017-09-21 16:29:52 +02001727 err = mmc_send_ext_csd(mmc, test_csd);
1728 if (err)
1729 return err;
1730
1731 /* Only compare read only fields */
1732 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1733 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1734 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1735 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1736 ext_csd[EXT_CSD_REV]
1737 == test_csd[EXT_CSD_REV] &&
1738 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1739 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1740 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1741 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1742 return 0;
1743
1744 return -EBADMSG;
1745}
1746
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001747#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001748static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1749 uint32_t allowed_mask)
1750{
1751 u32 card_mask = 0;
1752
1753 switch (mode) {
Peng Fan46801252018-08-10 14:07:54 +08001754 case MMC_HS_400:
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001755 case MMC_HS_200:
Peng Fan46801252018-08-10 14:07:54 +08001756 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
1757 EXT_CSD_CARD_TYPE_HS400_1_8V))
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001758 card_mask |= MMC_SIGNAL_VOLTAGE_180;
Peng Fan46801252018-08-10 14:07:54 +08001759 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1760 EXT_CSD_CARD_TYPE_HS400_1_2V))
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001761 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1762 break;
1763 case MMC_DDR_52:
1764 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1765 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1766 MMC_SIGNAL_VOLTAGE_180;
1767 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1768 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1769 break;
1770 default:
1771 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1772 break;
1773 }
1774
1775 while (card_mask & allowed_mask) {
1776 enum mmc_voltage best_match;
1777
1778 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1779 if (!mmc_set_signal_voltage(mmc, best_match))
1780 return 0;
1781
1782 allowed_mask &= ~best_match;
1783 }
1784
1785 return -ENOTSUPP;
1786}
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001787#else
1788static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1789 uint32_t allowed_mask)
1790{
1791 return 0;
1792}
1793#endif
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001794
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02001795static const struct mode_width_tuning mmc_modes_by_pref[] = {
Peng Fan46801252018-08-10 14:07:54 +08001796#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1797 {
1798 .mode = MMC_HS_400,
1799 .widths = MMC_MODE_8BIT,
1800 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1801 },
1802#endif
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001803#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02001804 {
1805 .mode = MMC_HS_200,
1806 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
Kishon Vijay Abraham I210369f2017-09-21 16:30:06 +02001807 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02001808 },
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001809#endif
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02001810 {
1811 .mode = MMC_DDR_52,
1812 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1813 },
1814 {
1815 .mode = MMC_HS_52,
1816 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1817 },
1818 {
1819 .mode = MMC_HS,
1820 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1821 },
1822 {
1823 .mode = MMC_LEGACY,
1824 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1825 }
1826};
1827
1828#define for_each_mmc_mode_by_pref(caps, mwt) \
1829 for (mwt = mmc_modes_by_pref;\
1830 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1831 mwt++) \
1832 if (caps & MMC_CAP(mwt->mode))
1833
1834static const struct ext_csd_bus_width {
1835 uint cap;
1836 bool is_ddr;
1837 uint ext_csd_bits;
1838} ext_csd_bus_width[] = {
1839 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1840 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1841 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1842 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1843 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1844};
1845
Peng Fan46801252018-08-10 14:07:54 +08001846#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1847static int mmc_select_hs400(struct mmc *mmc)
1848{
1849 int err;
1850
1851 /* Set timing to HS200 for tuning */
1852 err = mmc_set_card_speed(mmc, MMC_HS_200);
1853 if (err)
1854 return err;
1855
1856 /* configure the bus mode (host) */
1857 mmc_select_mode(mmc, MMC_HS_200);
1858 mmc_set_clock(mmc, mmc->tran_speed, false);
1859
1860 /* execute tuning if needed */
1861 err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
1862 if (err) {
1863 debug("tuning failed\n");
1864 return err;
1865 }
1866
1867 /* Set back to HS */
1868 mmc_set_card_speed(mmc, MMC_HS);
1869 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
1870
1871 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1872 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
1873 if (err)
1874 return err;
1875
1876 err = mmc_set_card_speed(mmc, MMC_HS_400);
1877 if (err)
1878 return err;
1879
1880 mmc_select_mode(mmc, MMC_HS_400);
1881 err = mmc_set_clock(mmc, mmc->tran_speed, false);
1882 if (err)
1883 return err;
1884
1885 return 0;
1886}
1887#else
1888static int mmc_select_hs400(struct mmc *mmc)
1889{
1890 return -ENOTSUPP;
1891}
1892#endif
1893
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02001894#define for_each_supported_width(caps, ddr, ecbv) \
1895 for (ecbv = ext_csd_bus_width;\
1896 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1897 ecbv++) \
1898 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1899
Jean-Jacques Hiblot3d30972b2017-09-21 16:30:09 +02001900static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
Jean-Jacques Hiblot933d1262017-09-21 16:29:52 +02001901{
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001902 int err;
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02001903 const struct mode_width_tuning *mwt;
1904 const struct ext_csd_bus_width *ecbw;
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001905
Jean-Jacques Hiblot93c31d12017-11-30 17:43:54 +01001906#ifdef DEBUG
1907 mmc_dump_capabilities("mmc", card_caps);
Jean-Jacques Hiblotd7e5e032017-11-30 17:43:57 +01001908 mmc_dump_capabilities("host", mmc->host_caps);
Jean-Jacques Hiblot93c31d12017-11-30 17:43:54 +01001909#endif
1910
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001911 /* Restrict card's capabilities by what the host can do */
Jean-Jacques Hiblotd7e5e032017-11-30 17:43:57 +01001912 card_caps &= mmc->host_caps;
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001913
1914 /* Only version 4 of MMC supports wider bus widths */
1915 if (mmc->version < MMC_VERSION_4)
1916 return 0;
1917
Jean-Jacques Hibloted9506b2017-09-21 16:29:51 +02001918 if (!mmc->ext_csd) {
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001919 pr_debug("No ext_csd found!\n"); /* this should enver happen */
Jean-Jacques Hibloted9506b2017-09-21 16:29:51 +02001920 return -ENOTSUPP;
1921 }
1922
Jaehoon Chung239cb2f2018-01-26 19:25:29 +09001923 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
Jean-Jacques Hiblot3d30972b2017-09-21 16:30:09 +02001924
1925 for_each_mmc_mode_by_pref(card_caps, mwt) {
1926 for_each_supported_width(card_caps & mwt->widths,
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02001927 mmc_is_mode_ddr(mwt->mode), ecbw) {
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001928 enum mmc_voltage old_voltage;
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09001929 pr_debug("trying mode %s width %d (at %d MHz)\n",
1930 mmc_mode_name(mwt->mode),
1931 bus_width(ecbw->cap),
1932 mmc_mode2freq(mmc, mwt->mode) / 1000000);
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001933 old_voltage = mmc->signal_voltage;
1934 err = mmc_set_lowest_voltage(mmc, mwt->mode,
1935 MMC_ALL_SIGNAL_VOLTAGE);
1936 if (err)
1937 continue;
1938
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02001939 /* configure the bus width (card + host) */
1940 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1941 EXT_CSD_BUS_WIDTH,
1942 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
1943 if (err)
1944 goto error;
1945 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001946
Peng Fan46801252018-08-10 14:07:54 +08001947 if (mwt->mode == MMC_HS_400) {
1948 err = mmc_select_hs400(mmc);
1949 if (err) {
1950 printf("Select HS400 failed %d\n", err);
1951 goto error;
1952 }
1953 } else {
1954 /* configure the bus speed (card) */
1955 err = mmc_set_card_speed(mmc, mwt->mode);
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02001956 if (err)
1957 goto error;
Peng Fan46801252018-08-10 14:07:54 +08001958
1959 /*
1960 * configure the bus width AND the ddr mode
1961 * (card). The host side will be taken care
1962 * of in the next step
1963 */
1964 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
1965 err = mmc_switch(mmc,
1966 EXT_CSD_CMD_SET_NORMAL,
1967 EXT_CSD_BUS_WIDTH,
1968 ecbw->ext_csd_bits);
1969 if (err)
1970 goto error;
1971 }
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001972
Peng Fan46801252018-08-10 14:07:54 +08001973 /* configure the bus mode (host) */
1974 mmc_select_mode(mmc, mwt->mode);
1975 mmc_set_clock(mmc, mmc->tran_speed,
1976 MMC_CLK_ENABLE);
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001977#ifdef MMC_SUPPORTS_TUNING
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02001978
Peng Fan46801252018-08-10 14:07:54 +08001979 /* execute tuning if needed */
1980 if (mwt->tuning) {
1981 err = mmc_execute_tuning(mmc,
1982 mwt->tuning);
1983 if (err) {
1984 pr_debug("tuning failed\n");
1985 goto error;
1986 }
Kishon Vijay Abraham I210369f2017-09-21 16:30:06 +02001987 }
Jean-Jacques Hiblot6051e782017-11-30 17:44:01 +01001988#endif
Peng Fan46801252018-08-10 14:07:54 +08001989 }
Kishon Vijay Abraham I210369f2017-09-21 16:30:06 +02001990
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02001991 /* do a transfer to check the configuration */
1992 err = mmc_read_and_compare_ext_csd(mmc);
1993 if (!err)
1994 return 0;
1995error:
Jean-Jacques Hiblotb6937d62017-09-21 16:30:11 +02001996 mmc_set_signal_voltage(mmc, old_voltage);
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02001997 /* if an error occured, revert to a safer bus mode */
1998 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1999 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2000 mmc_select_mode(mmc, MMC_LEGACY);
2001 mmc_set_bus_width(mmc, 1);
2002 }
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02002003 }
2004
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01002005 pr_err("unable to select a mode\n");
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02002006
Jean-Jacques Hiblotec346832017-09-21 16:29:58 +02002007 return -ENOTSUPP;
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02002008}
Marek Vasuta318a7a2018-04-15 00:37:11 +02002009#endif
2010
2011#if CONFIG_IS_ENABLED(MMC_TINY)
2012DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
2013#endif
Jean-Jacques Hiblot31e7cf32017-09-21 16:29:49 +02002014
Jean-Jacques Hibloted9506b2017-09-21 16:29:51 +02002015static int mmc_startup_v4(struct mmc *mmc)
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002016{
2017 int err, i;
2018 u64 capacity;
2019 bool has_parts = false;
2020 bool part_completed;
Jean-Jacques Hiblotfa6c5772018-01-04 15:23:31 +01002021 static const u32 mmc_versions[] = {
2022 MMC_VERSION_4,
2023 MMC_VERSION_4_1,
2024 MMC_VERSION_4_2,
2025 MMC_VERSION_4_3,
Jean-Jacques Hiblotc64862b2018-02-09 12:09:28 +01002026 MMC_VERSION_4_4,
Jean-Jacques Hiblotfa6c5772018-01-04 15:23:31 +01002027 MMC_VERSION_4_41,
2028 MMC_VERSION_4_5,
2029 MMC_VERSION_5_0,
2030 MMC_VERSION_5_1
2031 };
2032
Marek Vasuta318a7a2018-04-15 00:37:11 +02002033#if CONFIG_IS_ENABLED(MMC_TINY)
2034 u8 *ext_csd = ext_csd_bkup;
2035
2036 if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
2037 return 0;
2038
2039 if (!mmc->ext_csd)
2040 memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
2041
2042 err = mmc_send_ext_csd(mmc, ext_csd);
2043 if (err)
2044 goto error;
2045
2046 /* store the ext csd for future reference */
2047 if (!mmc->ext_csd)
2048 mmc->ext_csd = ext_csd;
2049#else
Jean-Jacques Hiblot06976eb2017-11-30 17:43:59 +01002050 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002051
2052 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2053 return 0;
2054
2055 /* check ext_csd version and capacity */
2056 err = mmc_send_ext_csd(mmc, ext_csd);
2057 if (err)
Jean-Jacques Hiblot06976eb2017-11-30 17:43:59 +01002058 goto error;
2059
2060 /* store the ext csd for future reference */
2061 if (!mmc->ext_csd)
2062 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2063 if (!mmc->ext_csd)
2064 return -ENOMEM;
2065 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
Marek Vasuta318a7a2018-04-15 00:37:11 +02002066#endif
Alexander Kochetkovf1133c92018-02-20 14:35:55 +03002067 if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
Jean-Jacques Hiblotfa6c5772018-01-04 15:23:31 +01002068 return -EINVAL;
2069
2070 mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2071
2072 if (mmc->version >= MMC_VERSION_4_2) {
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002073 /*
2074 * According to the JEDEC Standard, the value of
2075 * ext_csd's capacity is valid if the value is more
2076 * than 2GB
2077 */
2078 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2079 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2080 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2081 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2082 capacity *= MMC_MAX_BLOCK_LEN;
2083 if ((capacity >> 20) > 2 * 1024)
2084 mmc->capacity_user = capacity;
2085 }
2086
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002087 /* The partition data may be non-zero but it is only
2088 * effective if PARTITION_SETTING_COMPLETED is set in
2089 * EXT_CSD, so ignore any data if this bit is not set,
2090 * except for enabling the high-capacity group size
2091 * definition (see below).
2092 */
2093 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2094 EXT_CSD_PARTITION_SETTING_COMPLETED);
2095
2096 /* store the partition info of emmc */
2097 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2098 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2099 ext_csd[EXT_CSD_BOOT_MULT])
2100 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2101 if (part_completed &&
2102 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2103 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2104
2105 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2106
2107 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2108
2109 for (i = 0; i < 4; i++) {
2110 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2111 uint mult = (ext_csd[idx + 2] << 16) +
2112 (ext_csd[idx + 1] << 8) + ext_csd[idx];
2113 if (mult)
2114 has_parts = true;
2115 if (!part_completed)
2116 continue;
2117 mmc->capacity_gp[i] = mult;
2118 mmc->capacity_gp[i] *=
2119 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2120 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2121 mmc->capacity_gp[i] <<= 19;
2122 }
2123
Jean-Jacques Hiblotc94c5472018-01-04 15:23:35 +01002124#ifndef CONFIG_SPL_BUILD
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002125 if (part_completed) {
2126 mmc->enh_user_size =
2127 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2128 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2129 ext_csd[EXT_CSD_ENH_SIZE_MULT];
2130 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2131 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2132 mmc->enh_user_size <<= 19;
2133 mmc->enh_user_start =
2134 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2135 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2136 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2137 ext_csd[EXT_CSD_ENH_START_ADDR];
2138 if (mmc->high_capacity)
2139 mmc->enh_user_start <<= 9;
2140 }
Jean-Jacques Hiblotc94c5472018-01-04 15:23:35 +01002141#endif
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002142
2143 /*
2144 * Host needs to enable ERASE_GRP_DEF bit if device is
2145 * partitioned. This bit will be lost every time after a reset
2146 * or power off. This will affect erase size.
2147 */
2148 if (part_completed)
2149 has_parts = true;
2150 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2151 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2152 has_parts = true;
2153 if (has_parts) {
2154 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2155 EXT_CSD_ERASE_GROUP_DEF, 1);
2156
2157 if (err)
Jean-Jacques Hiblot06976eb2017-11-30 17:43:59 +01002158 goto error;
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002159
2160 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2161 }
2162
2163 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002164#if CONFIG_IS_ENABLED(MMC_WRITE)
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002165 /* Read out group size from ext_csd */
2166 mmc->erase_grp_size =
2167 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002168#endif
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002169 /*
2170 * if high capacity and partition setting completed
2171 * SEC_COUNT is valid even if it is smaller than 2 GiB
2172 * JEDEC Standard JESD84-B45, 6.2.4
2173 */
2174 if (mmc->high_capacity && part_completed) {
2175 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2176 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2177 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2178 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2179 capacity *= MMC_MAX_BLOCK_LEN;
2180 mmc->capacity_user = capacity;
2181 }
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002182 }
2183#if CONFIG_IS_ENABLED(MMC_WRITE)
2184 else {
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002185 /* Calculate the group size from the csd value. */
2186 int erase_gsz, erase_gmul;
2187
2188 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2189 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2190 mmc->erase_grp_size = (erase_gsz + 1)
2191 * (erase_gmul + 1);
2192 }
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002193#endif
Jean-Jacques Hiblotba54ab82018-01-04 15:23:36 +01002194#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002195 mmc->hc_wp_grp_size = 1024
2196 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2197 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
Jean-Jacques Hiblotba54ab82018-01-04 15:23:36 +01002198#endif
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002199
2200 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2201
2202 return 0;
Jean-Jacques Hiblot06976eb2017-11-30 17:43:59 +01002203error:
2204 if (mmc->ext_csd) {
Marek Vasuta318a7a2018-04-15 00:37:11 +02002205#if !CONFIG_IS_ENABLED(MMC_TINY)
Jean-Jacques Hiblot06976eb2017-11-30 17:43:59 +01002206 free(mmc->ext_csd);
Marek Vasuta318a7a2018-04-15 00:37:11 +02002207#endif
Jean-Jacques Hiblot06976eb2017-11-30 17:43:59 +01002208 mmc->ext_csd = NULL;
2209 }
2210 return err;
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002211}
2212
Kim Phillips87ea3892012-10-29 13:34:43 +00002213static int mmc_startup(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -05002214{
Stephen Warrene315ae82013-06-11 15:14:01 -06002215 int err, i;
Andy Flemingad347bb2008-10-30 16:41:01 -05002216 uint mult, freq;
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002217 u64 cmult, csize;
Andy Flemingad347bb2008-10-30 16:41:01 -05002218 struct mmc_cmd cmd;
Simon Glasse5db1152016-05-01 13:52:35 -06002219 struct blk_desc *bdesc;
Andy Flemingad347bb2008-10-30 16:41:01 -05002220
Thomas Chou1254c3d2010-12-24 13:12:21 +00002221#ifdef CONFIG_MMC_SPI_CRC_ON
2222 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2223 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2224 cmd.resp_type = MMC_RSP_R1;
2225 cmd.cmdarg = 1;
Thomas Chou1254c3d2010-12-24 13:12:21 +00002226 err = mmc_send_cmd(mmc, &cmd, NULL);
Thomas Chou1254c3d2010-12-24 13:12:21 +00002227 if (err)
2228 return err;
2229 }
2230#endif
2231
Andy Flemingad347bb2008-10-30 16:41:01 -05002232 /* Put the Card in Identify Mode */
Thomas Chou1254c3d2010-12-24 13:12:21 +00002233 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2234 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
Andy Flemingad347bb2008-10-30 16:41:01 -05002235 cmd.resp_type = MMC_RSP_R2;
2236 cmd.cmdarg = 0;
Andy Flemingad347bb2008-10-30 16:41:01 -05002237
2238 err = mmc_send_cmd(mmc, &cmd, NULL);
2239
Kishon Vijay Abraham I07baaa62017-09-21 16:30:10 +02002240#ifdef CONFIG_MMC_QUIRKS
2241 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2242 int retries = 4;
2243 /*
2244 * It has been seen that SEND_CID may fail on the first
2245 * attempt, let's try a few more time
2246 */
2247 do {
2248 err = mmc_send_cmd(mmc, &cmd, NULL);
2249 if (!err)
2250 break;
2251 } while (retries--);
2252 }
2253#endif
2254
Andy Flemingad347bb2008-10-30 16:41:01 -05002255 if (err)
2256 return err;
2257
2258 memcpy(mmc->cid, cmd.response, 16);
2259
2260 /*
2261 * For MMC cards, set the Relative Address.
2262 * For SD cards, get the Relatvie Address.
2263 * This also puts the cards into Standby State
2264 */
Thomas Chou1254c3d2010-12-24 13:12:21 +00002265 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2266 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2267 cmd.cmdarg = mmc->rca << 16;
2268 cmd.resp_type = MMC_RSP_R6;
Andy Flemingad347bb2008-10-30 16:41:01 -05002269
Thomas Chou1254c3d2010-12-24 13:12:21 +00002270 err = mmc_send_cmd(mmc, &cmd, NULL);
Andy Flemingad347bb2008-10-30 16:41:01 -05002271
Thomas Chou1254c3d2010-12-24 13:12:21 +00002272 if (err)
2273 return err;
Andy Flemingad347bb2008-10-30 16:41:01 -05002274
Thomas Chou1254c3d2010-12-24 13:12:21 +00002275 if (IS_SD(mmc))
2276 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2277 }
Andy Flemingad347bb2008-10-30 16:41:01 -05002278
2279 /* Get the Card-Specific Data */
2280 cmd.cmdidx = MMC_CMD_SEND_CSD;
2281 cmd.resp_type = MMC_RSP_R2;
2282 cmd.cmdarg = mmc->rca << 16;
Andy Flemingad347bb2008-10-30 16:41:01 -05002283
2284 err = mmc_send_cmd(mmc, &cmd, NULL);
2285
2286 if (err)
2287 return err;
2288
Rabin Vincentb6eed942009-04-05 13:30:56 +05302289 mmc->csd[0] = cmd.response[0];
2290 mmc->csd[1] = cmd.response[1];
2291 mmc->csd[2] = cmd.response[2];
2292 mmc->csd[3] = cmd.response[3];
Andy Flemingad347bb2008-10-30 16:41:01 -05002293
2294 if (mmc->version == MMC_VERSION_UNKNOWN) {
Rabin Vincentbdf7a682009-04-05 13:30:55 +05302295 int version = (cmd.response[0] >> 26) & 0xf;
Andy Flemingad347bb2008-10-30 16:41:01 -05002296
2297 switch (version) {
Bin Meng4a4ef872016-03-17 21:53:13 -07002298 case 0:
2299 mmc->version = MMC_VERSION_1_2;
2300 break;
2301 case 1:
2302 mmc->version = MMC_VERSION_1_4;
2303 break;
2304 case 2:
2305 mmc->version = MMC_VERSION_2_2;
2306 break;
2307 case 3:
2308 mmc->version = MMC_VERSION_3;
2309 break;
2310 case 4:
2311 mmc->version = MMC_VERSION_4;
2312 break;
2313 default:
2314 mmc->version = MMC_VERSION_1_2;
2315 break;
Andy Flemingad347bb2008-10-30 16:41:01 -05002316 }
2317 }
2318
2319 /* divide frequency by 10, since the mults are 10x bigger */
Rabin Vincentbdf7a682009-04-05 13:30:55 +05302320 freq = fbase[(cmd.response[0] & 0x7)];
2321 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
Andy Flemingad347bb2008-10-30 16:41:01 -05002322
Jean-Jacques Hiblota94fb412017-09-21 16:29:53 +02002323 mmc->legacy_speed = freq * mult;
Jean-Jacques Hiblota94fb412017-09-21 16:29:53 +02002324 mmc_select_mode(mmc, MMC_LEGACY);
Andy Flemingad347bb2008-10-30 16:41:01 -05002325
Markus Niebel03951412013-12-16 13:40:46 +01002326 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
Rabin Vincentb6eed942009-04-05 13:30:56 +05302327 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002328#if CONFIG_IS_ENABLED(MMC_WRITE)
Andy Flemingad347bb2008-10-30 16:41:01 -05002329
2330 if (IS_SD(mmc))
2331 mmc->write_bl_len = mmc->read_bl_len;
2332 else
Rabin Vincentb6eed942009-04-05 13:30:56 +05302333 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002334#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05002335
2336 if (mmc->high_capacity) {
2337 csize = (mmc->csd[1] & 0x3f) << 16
2338 | (mmc->csd[2] & 0xffff0000) >> 16;
2339 cmult = 8;
2340 } else {
2341 csize = (mmc->csd[1] & 0x3ff) << 2
2342 | (mmc->csd[2] & 0xc0000000) >> 30;
2343 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2344 }
2345
Stephen Warrene315ae82013-06-11 15:14:01 -06002346 mmc->capacity_user = (csize + 1) << (cmult + 2);
2347 mmc->capacity_user *= mmc->read_bl_len;
2348 mmc->capacity_boot = 0;
2349 mmc->capacity_rpmb = 0;
2350 for (i = 0; i < 4; i++)
2351 mmc->capacity_gp[i] = 0;
Andy Flemingad347bb2008-10-30 16:41:01 -05002352
Simon Glassa09c2b72013-04-03 08:54:30 +00002353 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2354 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
Andy Flemingad347bb2008-10-30 16:41:01 -05002355
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002356#if CONFIG_IS_ENABLED(MMC_WRITE)
Simon Glassa09c2b72013-04-03 08:54:30 +00002357 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2358 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002359#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05002360
Markus Niebel03951412013-12-16 13:40:46 +01002361 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2362 cmd.cmdidx = MMC_CMD_SET_DSR;
2363 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2364 cmd.resp_type = MMC_RSP_NONE;
2365 if (mmc_send_cmd(mmc, &cmd, NULL))
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01002366 pr_warn("MMC: SET_DSR failed\n");
Markus Niebel03951412013-12-16 13:40:46 +01002367 }
2368
Andy Flemingad347bb2008-10-30 16:41:01 -05002369 /* Select the card, and put it into Transfer Mode */
Thomas Chou1254c3d2010-12-24 13:12:21 +00002370 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2371 cmd.cmdidx = MMC_CMD_SELECT_CARD;
Ajay Bhargav4a32fba2011-10-05 03:13:23 +00002372 cmd.resp_type = MMC_RSP_R1;
Thomas Chou1254c3d2010-12-24 13:12:21 +00002373 cmd.cmdarg = mmc->rca << 16;
Thomas Chou1254c3d2010-12-24 13:12:21 +00002374 err = mmc_send_cmd(mmc, &cmd, NULL);
Andy Flemingad347bb2008-10-30 16:41:01 -05002375
Thomas Chou1254c3d2010-12-24 13:12:21 +00002376 if (err)
2377 return err;
2378 }
Andy Flemingad347bb2008-10-30 16:41:01 -05002379
Lei Wenea526762011-06-22 17:03:31 +00002380 /*
2381 * For SD, its erase group is always one sector
2382 */
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002383#if CONFIG_IS_ENABLED(MMC_WRITE)
Lei Wenea526762011-06-22 17:03:31 +00002384 mmc->erase_grp_size = 1;
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002385#endif
Lei Wen31b99802011-05-02 16:26:26 +00002386 mmc->part_config = MMCPART_NOAVAILABLE;
Diego Santa Cruza7a75992014-12-23 10:50:27 +01002387
Jean-Jacques Hibloted9506b2017-09-21 16:29:51 +02002388 err = mmc_startup_v4(mmc);
Jean-Jacques Hiblote84459c2017-09-21 16:29:50 +02002389 if (err)
2390 return err;
Sukumar Ghorai232293c2010-09-20 18:29:29 +05302391
Simon Glasse5db1152016-05-01 13:52:35 -06002392 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
Stephen Warrene315ae82013-06-11 15:14:01 -06002393 if (err)
2394 return err;
2395
Marek Vasuta318a7a2018-04-15 00:37:11 +02002396#if CONFIG_IS_ENABLED(MMC_TINY)
2397 mmc_set_clock(mmc, mmc->legacy_speed, false);
2398 mmc_select_mode(mmc, IS_SD(mmc) ? SD_LEGACY : MMC_LEGACY);
2399 mmc_set_bus_width(mmc, 1);
2400#else
Jean-Jacques Hiblot3d30972b2017-09-21 16:30:09 +02002401 if (IS_SD(mmc)) {
2402 err = sd_get_capabilities(mmc);
2403 if (err)
2404 return err;
2405 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2406 } else {
2407 err = mmc_get_capabilities(mmc);
2408 if (err)
2409 return err;
2410 mmc_select_mode_and_width(mmc, mmc->card_caps);
2411 }
Marek Vasuta318a7a2018-04-15 00:37:11 +02002412#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05002413 if (err)
2414 return err;
2415
Jean-Jacques Hiblot3d30972b2017-09-21 16:30:09 +02002416 mmc->best_mode = mmc->selected_mode;
Jaehoon Chunge1d4c7b2012-03-26 21:16:03 +00002417
Andrew Gabbasov532663b2014-12-01 06:59:11 -06002418 /* Fix the block length for DDR mode */
2419 if (mmc->ddr_mode) {
2420 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002421#if CONFIG_IS_ENABLED(MMC_WRITE)
Andrew Gabbasov532663b2014-12-01 06:59:11 -06002422 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
Jean-Jacques Hiblot27edffe2018-01-04 15:23:34 +01002423#endif
Andrew Gabbasov532663b2014-12-01 06:59:11 -06002424 }
2425
Andy Flemingad347bb2008-10-30 16:41:01 -05002426 /* fill in device description */
Simon Glasse5db1152016-05-01 13:52:35 -06002427 bdesc = mmc_get_blk_desc(mmc);
2428 bdesc->lun = 0;
2429 bdesc->hwpart = 0;
2430 bdesc->type = 0;
2431 bdesc->blksz = mmc->read_bl_len;
2432 bdesc->log2blksz = LOG2(bdesc->blksz);
2433 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
Sjoerd Simonsd67754f2015-12-04 23:27:40 +01002434#if !defined(CONFIG_SPL_BUILD) || \
2435 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2436 !defined(CONFIG_USE_TINY_PRINTF))
Simon Glasse5db1152016-05-01 13:52:35 -06002437 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
Taylor Hutt7367ec22012-10-20 17:15:59 +00002438 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2439 (mmc->cid[3] >> 16) & 0xffff);
Simon Glasse5db1152016-05-01 13:52:35 -06002440 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
Taylor Hutt7367ec22012-10-20 17:15:59 +00002441 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2442 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2443 (mmc->cid[2] >> 24) & 0xff);
Simon Glasse5db1152016-05-01 13:52:35 -06002444 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
Taylor Hutt7367ec22012-10-20 17:15:59 +00002445 (mmc->cid[2] >> 16) & 0xf);
Paul Burton6a7c5ba2013-09-04 16:12:25 +01002446#else
Simon Glasse5db1152016-05-01 13:52:35 -06002447 bdesc->vendor[0] = 0;
2448 bdesc->product[0] = 0;
2449 bdesc->revision[0] = 0;
Paul Burton6a7c5ba2013-09-04 16:12:25 +01002450#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05002451
2452 return 0;
2453}
2454
Kim Phillips87ea3892012-10-29 13:34:43 +00002455static int mmc_send_if_cond(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -05002456{
2457 struct mmc_cmd cmd;
2458 int err;
2459
2460 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2461 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
Pantelis Antoniou2c850462014-03-11 19:34:20 +02002462 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
Andy Flemingad347bb2008-10-30 16:41:01 -05002463 cmd.resp_type = MMC_RSP_R7;
Andy Flemingad347bb2008-10-30 16:41:01 -05002464
2465 err = mmc_send_cmd(mmc, &cmd, NULL);
2466
2467 if (err)
2468 return err;
2469
Rabin Vincentb6eed942009-04-05 13:30:56 +05302470 if ((cmd.response[0] & 0xff) != 0xaa)
Jaehoon Chung7825d202016-07-19 16:33:36 +09002471 return -EOPNOTSUPP;
Andy Flemingad347bb2008-10-30 16:41:01 -05002472 else
2473 mmc->version = SD_VERSION_2;
2474
2475 return 0;
2476}
2477
Simon Glass5f4bd8c2017-07-04 13:31:19 -06002478#if !CONFIG_IS_ENABLED(DM_MMC)
Paul Kocialkowski2439fe92014-11-08 20:55:45 +01002479/* board-specific MMC power initializations. */
2480__weak void board_mmc_power_init(void)
2481{
2482}
Simon Glass833b80d2017-04-22 19:10:56 -06002483#endif
Paul Kocialkowski2439fe92014-11-08 20:55:45 +01002484
Peng Fan15305962016-10-11 15:08:43 +08002485static int mmc_power_init(struct mmc *mmc)
2486{
Simon Glass5f4bd8c2017-07-04 13:31:19 -06002487#if CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblota49ffa12017-09-21 16:29:48 +02002488#if CONFIG_IS_ENABLED(DM_REGULATOR)
Peng Fan15305962016-10-11 15:08:43 +08002489 int ret;
2490
2491 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
Jean-Jacques Hiblota49ffa12017-09-21 16:29:48 +02002492 &mmc->vmmc_supply);
2493 if (ret)
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09002494 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
Jean-Jacques Hiblota49ffa12017-09-21 16:29:48 +02002495
2496 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2497 &mmc->vqmmc_supply);
2498 if (ret)
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09002499 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002500#endif
2501#else /* !CONFIG_DM_MMC */
2502 /*
2503 * Driver model should use a regulator, as above, rather than calling
2504 * out to board code.
2505 */
2506 board_mmc_power_init();
2507#endif
2508 return 0;
2509}
2510
2511/*
2512 * put the host in the initial state:
2513 * - turn on Vdd (card power supply)
2514 * - configure the bus width and clock to minimal values
2515 */
2516static void mmc_set_initial_state(struct mmc *mmc)
2517{
2518 int err;
2519
2520 /* First try to set 3.3V. If it fails set to 1.8V */
2521 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2522 if (err != 0)
2523 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2524 if (err != 0)
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01002525 pr_warn("mmc: failed to set signal voltage\n");
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002526
2527 mmc_select_mode(mmc, MMC_LEGACY);
2528 mmc_set_bus_width(mmc, 1);
Jaehoon Chung239cb2f2018-01-26 19:25:29 +09002529 mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002530}
Peng Fan15305962016-10-11 15:08:43 +08002531
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002532static int mmc_power_on(struct mmc *mmc)
2533{
2534#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
Jean-Jacques Hiblota49ffa12017-09-21 16:29:48 +02002535 if (mmc->vmmc_supply) {
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002536 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2537
Jean-Jacques Hiblota49ffa12017-09-21 16:29:48 +02002538 if (ret) {
2539 puts("Error enabling VMMC supply\n");
2540 return ret;
2541 }
Peng Fan15305962016-10-11 15:08:43 +08002542 }
2543#endif
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002544 return 0;
2545}
2546
2547static int mmc_power_off(struct mmc *mmc)
2548{
Jaehoon Chung239cb2f2018-01-26 19:25:29 +09002549 mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002550#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2551 if (mmc->vmmc_supply) {
2552 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2553
2554 if (ret) {
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09002555 pr_debug("Error disabling VMMC supply\n");
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002556 return ret;
2557 }
2558 }
Simon Glass833b80d2017-04-22 19:10:56 -06002559#endif
Peng Fan15305962016-10-11 15:08:43 +08002560 return 0;
2561}
2562
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002563static int mmc_power_cycle(struct mmc *mmc)
2564{
2565 int ret;
2566
2567 ret = mmc_power_off(mmc);
2568 if (ret)
2569 return ret;
2570 /*
2571 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2572 * to be on the safer side.
2573 */
2574 udelay(2000);
2575 return mmc_power_on(mmc);
2576}
2577
Jon Nettleton2663fe42018-06-11 15:26:19 +03002578int mmc_get_op_cond(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -05002579{
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02002580 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
Macpaul Lin028bde12011-11-14 23:35:39 +00002581 int err;
Andy Flemingad347bb2008-10-30 16:41:01 -05002582
Lei Wen31b99802011-05-02 16:26:26 +00002583 if (mmc->has_init)
2584 return 0;
2585
Yangbo Lub124f8a2015-04-22 13:57:00 +08002586#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2587 mmc_adapter_card_type_ident();
2588#endif
Peng Fan15305962016-10-11 15:08:43 +08002589 err = mmc_power_init(mmc);
2590 if (err)
2591 return err;
Paul Kocialkowski2439fe92014-11-08 20:55:45 +01002592
Kishon Vijay Abraham I07baaa62017-09-21 16:30:10 +02002593#ifdef CONFIG_MMC_QUIRKS
2594 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2595 MMC_QUIRK_RETRY_SEND_CID;
2596#endif
2597
Jean-Jacques Hiblotdc030fb2017-09-21 16:30:08 +02002598 err = mmc_power_cycle(mmc);
2599 if (err) {
2600 /*
2601 * if power cycling is not supported, we should not try
2602 * to use the UHS modes, because we wouldn't be able to
2603 * recover from an error during the UHS initialization.
2604 */
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09002605 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
Jean-Jacques Hiblotdc030fb2017-09-21 16:30:08 +02002606 uhs_en = false;
2607 mmc->host_caps &= ~UHS_CAPS;
2608 err = mmc_power_on(mmc);
2609 }
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002610 if (err)
2611 return err;
2612
Simon Glasseba48f92017-07-29 11:35:31 -06002613#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glass394dfc02016-06-12 23:30:22 -06002614 /* The device has already been probed ready for use */
2615#else
Pantelis Antoniouc9e75912014-02-26 19:28:45 +02002616 /* made sure it's not NULL earlier */
Pantelis Antoniou2c850462014-03-11 19:34:20 +02002617 err = mmc->cfg->ops->init(mmc);
Andy Flemingad347bb2008-10-30 16:41:01 -05002618 if (err)
2619 return err;
Simon Glass394dfc02016-06-12 23:30:22 -06002620#endif
Andrew Gabbasov9fc2a412014-12-01 06:59:09 -06002621 mmc->ddr_mode = 0;
Kishon Vijay Abraham I4afb12b2017-09-21 16:30:00 +02002622
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02002623retry:
Kishon Vijay Abraham I80b87e12017-09-21 16:30:02 +02002624 mmc_set_initial_state(mmc);
Jean-Jacques Hiblot5f23d872017-09-21 16:30:01 +02002625 mmc_send_init_stream(mmc);
2626
Andy Flemingad347bb2008-10-30 16:41:01 -05002627 /* Reset the Card */
2628 err = mmc_go_idle(mmc);
2629
2630 if (err)
2631 return err;
2632
Lei Wen31b99802011-05-02 16:26:26 +00002633 /* The internal partition reset to user partition(0) at every CMD0*/
Simon Glasse5db1152016-05-01 13:52:35 -06002634 mmc_get_blk_desc(mmc)->hwpart = 0;
Lei Wen31b99802011-05-02 16:26:26 +00002635
Andy Flemingad347bb2008-10-30 16:41:01 -05002636 /* Test for SD version 2 */
Macpaul Lin028bde12011-11-14 23:35:39 +00002637 err = mmc_send_if_cond(mmc);
Andy Flemingad347bb2008-10-30 16:41:01 -05002638
Andy Flemingad347bb2008-10-30 16:41:01 -05002639 /* Now try to get the SD card's operating condition */
Jean-Jacques Hiblotf4d5b3e2017-09-21 16:30:07 +02002640 err = sd_send_op_cond(mmc, uhs_en);
2641 if (err && uhs_en) {
2642 uhs_en = false;
2643 mmc_power_cycle(mmc);
2644 goto retry;
2645 }
Andy Flemingad347bb2008-10-30 16:41:01 -05002646
2647 /* If the command timed out, we check for an MMC card */
Jaehoon Chung7825d202016-07-19 16:33:36 +09002648 if (err == -ETIMEDOUT) {
Andy Flemingad347bb2008-10-30 16:41:01 -05002649 err = mmc_send_op_cond(mmc);
2650
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -05002651 if (err) {
Paul Burton6a7c5ba2013-09-04 16:12:25 +01002652#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01002653 pr_err("Card did not respond to voltage select!\n");
Paul Burton6a7c5ba2013-09-04 16:12:25 +01002654#endif
Jaehoon Chung7825d202016-07-19 16:33:36 +09002655 return -EOPNOTSUPP;
Andy Flemingad347bb2008-10-30 16:41:01 -05002656 }
2657 }
2658
Jon Nettleton2663fe42018-06-11 15:26:19 +03002659 return err;
2660}
2661
2662int mmc_start_init(struct mmc *mmc)
2663{
2664 bool no_card;
2665 int err = 0;
2666
2667 /*
2668 * all hosts are capable of 1 bit bus-width and able to use the legacy
2669 * timings.
2670 */
2671 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
2672 MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
2673
2674#if !defined(CONFIG_MMC_BROKEN_CD)
2675 /* we pretend there's no card when init is NULL */
2676 no_card = mmc_getcd(mmc) == 0;
2677#else
2678 no_card = 0;
2679#endif
2680#if !CONFIG_IS_ENABLED(DM_MMC)
2681 no_card = no_card || (mmc->cfg->ops->init == NULL);
2682#endif
2683 if (no_card) {
2684 mmc->has_init = 0;
2685#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2686 pr_err("MMC: no card present\n");
2687#endif
2688 return -ENOMEDIUM;
2689 }
2690
2691 err = mmc_get_op_cond(mmc);
2692
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -05002693 if (!err)
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002694 mmc->init_in_progress = 1;
2695
2696 return err;
2697}
2698
2699static int mmc_complete_init(struct mmc *mmc)
2700{
2701 int err = 0;
2702
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -05002703 mmc->init_in_progress = 0;
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002704 if (mmc->op_cond_pending)
2705 err = mmc_complete_op_cond(mmc);
2706
2707 if (!err)
2708 err = mmc_startup(mmc);
Lei Wen31b99802011-05-02 16:26:26 +00002709 if (err)
2710 mmc->has_init = 0;
2711 else
2712 mmc->has_init = 1;
2713 return err;
Andy Flemingad347bb2008-10-30 16:41:01 -05002714}
2715
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002716int mmc_init(struct mmc *mmc)
2717{
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -05002718 int err = 0;
Vipul Kumardbad7b42018-05-03 12:20:54 +05302719 __maybe_unused ulong start;
Simon Glass5f4bd8c2017-07-04 13:31:19 -06002720#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glass59bc6f22016-05-01 13:52:41 -06002721 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002722
Simon Glass59bc6f22016-05-01 13:52:41 -06002723 upriv->mmc = mmc;
2724#endif
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002725 if (mmc->has_init)
2726 return 0;
Mateusz Zalegada351782014-04-29 20:15:30 +02002727
2728 start = get_timer(0);
2729
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002730 if (!mmc->init_in_progress)
2731 err = mmc_start_init(mmc);
2732
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -05002733 if (!err)
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002734 err = mmc_complete_init(mmc);
Jagan Teki9bee2b52017-01-10 11:18:43 +01002735 if (err)
Masahiro Yamadaf97b1482018-01-28 19:11:42 +09002736 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
Jagan Teki9bee2b52017-01-10 11:18:43 +01002737
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002738 return err;
2739}
2740
Markus Niebel03951412013-12-16 13:40:46 +01002741int mmc_set_dsr(struct mmc *mmc, u16 val)
2742{
2743 mmc->dsr = val;
2744 return 0;
2745}
2746
Jeroen Hofstee47726302014-07-10 22:46:28 +02002747/* CPU-specific MMC initializations */
2748__weak int cpu_mmc_init(bd_t *bis)
Andy Flemingad347bb2008-10-30 16:41:01 -05002749{
2750 return -1;
2751}
2752
Jeroen Hofstee47726302014-07-10 22:46:28 +02002753/* board-specific MMC initializations. */
2754__weak int board_mmc_init(bd_t *bis)
2755{
2756 return -1;
2757}
Andy Flemingad347bb2008-10-30 16:41:01 -05002758
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002759void mmc_set_preinit(struct mmc *mmc, int preinit)
2760{
2761 mmc->preinit = preinit;
2762}
2763
Faiz Abbasb3857fd2018-02-12 19:35:24 +05302764#if CONFIG_IS_ENABLED(DM_MMC)
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06002765static int mmc_probe(bd_t *bis)
2766{
Simon Glass547cb342015-12-29 05:22:49 -07002767 int ret, i;
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06002768 struct uclass *uc;
Simon Glass547cb342015-12-29 05:22:49 -07002769 struct udevice *dev;
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06002770
2771 ret = uclass_get(UCLASS_MMC, &uc);
2772 if (ret)
2773 return ret;
2774
Simon Glass547cb342015-12-29 05:22:49 -07002775 /*
2776 * Try to add them in sequence order. Really with driver model we
2777 * should allow holes, but the current MMC list does not allow that.
2778 * So if we request 0, 1, 3 we will get 0, 1, 2.
2779 */
2780 for (i = 0; ; i++) {
2781 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2782 if (ret == -ENODEV)
2783 break;
2784 }
2785 uclass_foreach_dev(dev, uc) {
2786 ret = device_probe(dev);
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06002787 if (ret)
Jean-Jacques Hiblot678b6082017-11-30 17:44:00 +01002788 pr_err("%s - probe failed: %d\n", dev->name, ret);
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06002789 }
2790
2791 return 0;
2792}
2793#else
2794static int mmc_probe(bd_t *bis)
2795{
2796 if (board_mmc_init(bis) < 0)
2797 cpu_mmc_init(bis);
2798
2799 return 0;
2800}
2801#endif
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00002802
Andy Flemingad347bb2008-10-30 16:41:01 -05002803int mmc_initialize(bd_t *bis)
2804{
Daniel Kochmański13df57b2015-05-29 16:55:43 +02002805 static int initialized = 0;
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06002806 int ret;
Daniel Kochmański13df57b2015-05-29 16:55:43 +02002807 if (initialized) /* Avoid initializing mmc multiple times */
2808 return 0;
2809 initialized = 1;
2810
Simon Glass5f4bd8c2017-07-04 13:31:19 -06002811#if !CONFIG_IS_ENABLED(BLK)
Marek Vasutf537e392016-12-01 02:06:33 +01002812#if !CONFIG_IS_ENABLED(MMC_TINY)
Simon Glasse5db1152016-05-01 13:52:35 -06002813 mmc_list_init();
2814#endif
Marek Vasutf537e392016-12-01 02:06:33 +01002815#endif
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06002816 ret = mmc_probe(bis);
2817 if (ret)
2818 return ret;
Andy Flemingad347bb2008-10-30 16:41:01 -05002819
Ying Zhang9ff70262013-08-16 15:16:11 +08002820#ifndef CONFIG_SPL_BUILD
Andy Flemingad347bb2008-10-30 16:41:01 -05002821 print_mmc_devices(',');
Ying Zhang9ff70262013-08-16 15:16:11 +08002822#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05002823
Simon Glasse5db1152016-05-01 13:52:35 -06002824 mmc_do_preinit();
Andy Flemingad347bb2008-10-30 16:41:01 -05002825 return 0;
2826}
Tomas Melinc17dae52016-11-25 11:01:03 +02002827
2828#ifdef CONFIG_CMD_BKOPS_ENABLE
2829int mmc_set_bkops_enable(struct mmc *mmc)
2830{
2831 int err;
2832 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2833
2834 err = mmc_send_ext_csd(mmc, ext_csd);
2835 if (err) {
2836 puts("Could not get ext_csd register values\n");
2837 return err;
2838 }
2839
2840 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2841 puts("Background operations not supported on device\n");
2842 return -EMEDIUMTYPE;
2843 }
2844
2845 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2846 puts("Background operations already enabled\n");
2847 return 0;
2848 }
2849
2850 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2851 if (err) {
2852 puts("Failed to enable manual background operations\n");
2853 return err;
2854 }
2855
2856 puts("Enabled manual background operations\n");
2857
2858 return 0;
2859}
2860#endif