blob: 0df551f94cce09167a072125f1f98c67ec3fdf50 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass11d7a5b2013-04-17 16:13:36 +00002/*
3 * Copyright (c) 2012 The Chromium OS Authors.
4 *
Bin Meng49f70992014-11-09 22:19:13 +08005 * TSC calibration codes are adapted from Linux kernel
6 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
Simon Glass11d7a5b2013-04-17 16:13:36 +00007 */
8
9#include <common.h>
Bin Meng976c2e82015-11-13 00:11:21 -080010#include <dm.h>
Simon Glass11d7a5b2013-04-17 16:13:36 +000011#include <malloc.h>
Simon Glass495a5dc2019-11-14 12:57:30 -070012#include <time.h>
Bin Meng976c2e82015-11-13 00:11:21 -080013#include <timer.h>
Bin Mengd159ffb2017-07-25 20:12:01 -070014#include <asm/cpu.h>
Simon Glass11d7a5b2013-04-17 16:13:36 +000015#include <asm/io.h>
16#include <asm/i8254.h>
17#include <asm/ibmpc.h>
18#include <asm/msr.h>
19#include <asm/u-boot-x86.h>
20
Bin Meng7943dc22017-08-15 22:41:50 -070021#define MAX_NUM_FREQS 9
Bin Meng49f70992014-11-09 22:19:13 +080022
Bernhard Messerklinger0576f552019-01-07 12:14:40 +010023#define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
24#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
25#define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
26#define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
27#define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
28#define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
29
Simon Glass11d7a5b2013-04-17 16:13:36 +000030DECLARE_GLOBAL_DATA_PTR;
31
Bernhard Messerklinger0576f552019-01-07 12:14:40 +010032/*
33 * native_calibrate_tsc
34 * Determine TSC frequency via CPUID, else return 0.
35 */
36static unsigned long native_calibrate_tsc(void)
37{
38 struct cpuid_result tsc_info;
39 unsigned int crystal_freq;
40
41 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
42 return 0;
43
44 if (cpuid_eax(0) < 0x15)
45 return 0;
46
47 tsc_info = cpuid(0x15);
48
49 if (tsc_info.ebx == 0 || tsc_info.eax == 0)
50 return 0;
51
52 crystal_freq = tsc_info.ecx / 1000;
53
54 if (!crystal_freq) {
55 switch (gd->arch.x86_model) {
56 case INTEL_FAM6_SKYLAKE_MOBILE:
57 case INTEL_FAM6_SKYLAKE_DESKTOP:
58 case INTEL_FAM6_KABYLAKE_MOBILE:
59 case INTEL_FAM6_KABYLAKE_DESKTOP:
60 crystal_freq = 24000; /* 24.0 MHz */
61 break;
62 case INTEL_FAM6_ATOM_GOLDMONT_X:
63 crystal_freq = 25000; /* 25.0 MHz */
64 break;
65 case INTEL_FAM6_ATOM_GOLDMONT:
66 crystal_freq = 19200; /* 19.2 MHz */
67 break;
68 default:
69 return 0;
70 }
71 }
72
73 return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
74}
75
Christian Gmeiner1b1472a2018-05-14 11:32:17 +020076static unsigned long cpu_mhz_from_cpuid(void)
77{
78 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
79 return 0;
80
81 if (cpuid_eax(0) < 0x16)
82 return 0;
83
84 return cpuid_eax(0x16);
85}
86
Bin Meng49f70992014-11-09 22:19:13 +080087/*
88 * According to Intel 64 and IA-32 System Programming Guide,
89 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
90 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
91 * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
92 * so we need manually differentiate SoC families. This is what the
93 * field msr_plat does.
94 */
95struct freq_desc {
96 u8 x86_family; /* CPU family */
97 u8 x86_model; /* model */
Simon Glass40a8c352014-11-12 22:42:04 -070098 /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
99 u8 msr_plat;
Bin Meng49f70992014-11-09 22:19:13 +0800100 u32 freqs[MAX_NUM_FREQS];
101};
102
103static struct freq_desc freq_desc_tables[] = {
104 /* PNW */
Bin Meng7943dc22017-08-15 22:41:50 -0700105 { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
Bin Meng49f70992014-11-09 22:19:13 +0800106 /* CLV+ */
Bin Meng7943dc22017-08-15 22:41:50 -0700107 { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
Bin Mengaeb581a2017-07-25 20:12:03 -0700108 /* TNG - Intel Atom processor Z3400 series */
Bin Meng7943dc22017-08-15 22:41:50 -0700109 { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
Bin Mengaeb581a2017-07-25 20:12:03 -0700110 /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
Bin Meng7943dc22017-08-15 22:41:50 -0700111 { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
Bin Mengaeb581a2017-07-25 20:12:03 -0700112 /* ANN - Intel Atom processor Z3500 series */
Bin Meng7943dc22017-08-15 22:41:50 -0700113 { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
114 /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
115 { 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
116 80000, 93300, 90000, 88900, 87500 } },
Simon Glass40a8c352014-11-12 22:42:04 -0700117 /* Ivybridge */
Bin Meng7943dc22017-08-15 22:41:50 -0700118 { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
Bin Meng49f70992014-11-09 22:19:13 +0800119};
120
121static int match_cpu(u8 family, u8 model)
122{
123 int i;
124
125 for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
126 if ((family == freq_desc_tables[i].x86_family) &&
127 (model == freq_desc_tables[i].x86_model))
128 return i;
129 }
130
131 return -1;
132}
133
134/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
135#define id_to_freq(cpu_index, freq_id) \
136 (freq_desc_tables[cpu_index].freqs[freq_id])
137
138/*
Bin Meng6ffad642017-07-25 20:12:05 -0700139 * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
140 * reliable and the frequency is known (provided by HW).
Bin Meng49f70992014-11-09 22:19:13 +0800141 *
Bin Meng6ffad642017-07-25 20:12:05 -0700142 * On these platforms PIT/HPET is generally not available so calibration won't
143 * work at all and there is no other clocksource to act as a watchdog for the
144 * TSC, so we have no other choice than to trust it.
145 *
146 * Returns the TSC frequency in MHz or 0 if HW does not provide it.
Bin Meng49f70992014-11-09 22:19:13 +0800147 */
Bin Meng6ffad642017-07-25 20:12:05 -0700148static unsigned long __maybe_unused cpu_mhz_from_msr(void)
Bin Meng49f70992014-11-09 22:19:13 +0800149{
150 u32 lo, hi, ratio, freq_id, freq;
151 unsigned long res;
152 int cpu_index;
153
Bin Mengd159ffb2017-07-25 20:12:01 -0700154 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
155 return 0;
156
Bin Meng49f70992014-11-09 22:19:13 +0800157 cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
158 if (cpu_index < 0)
159 return 0;
160
161 if (freq_desc_tables[cpu_index].msr_plat) {
162 rdmsr(MSR_PLATFORM_INFO, lo, hi);
Bin Mengf4ed4d72017-07-25 20:12:00 -0700163 ratio = (lo >> 8) & 0xff;
Bin Meng49f70992014-11-09 22:19:13 +0800164 } else {
165 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
166 ratio = (hi >> 8) & 0x1f;
167 }
168 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
169
Simon Glass40a8c352014-11-12 22:42:04 -0700170 if (freq_desc_tables[cpu_index].msr_plat == 2) {
171 /* TODO: Figure out how best to deal with this */
Bin Meng23ee9ab2017-07-25 20:12:04 -0700172 freq = 100000;
Simon Glass40a8c352014-11-12 22:42:04 -0700173 debug("Using frequency: %u KHz\n", freq);
174 } else {
175 /* Get FSB FREQ ID */
176 rdmsr(MSR_FSB_FREQ, lo, hi);
177 freq_id = lo & 0x7;
178 freq = id_to_freq(cpu_index, freq_id);
179 debug("Resolved frequency ID: %u, frequency: %u KHz\n",
180 freq_id, freq);
181 }
Bin Meng49f70992014-11-09 22:19:13 +0800182
183 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
184 res = freq * ratio / 1000;
185 debug("TSC runs at %lu MHz\n", res);
186
187 return res;
Bin Meng49f70992014-11-09 22:19:13 +0800188}
189
Bin Mengbba97052014-11-09 22:19:25 +0800190/*
191 * This reads the current MSB of the PIT counter, and
192 * checks if we are running on sufficiently fast and
193 * non-virtualized hardware.
194 *
195 * Our expectations are:
196 *
197 * - the PIT is running at roughly 1.19MHz
198 *
199 * - each IO is going to take about 1us on real hardware,
200 * but we allow it to be much faster (by a factor of 10) or
201 * _slightly_ slower (ie we allow up to a 2us read+counter
202 * update - anything else implies a unacceptably slow CPU
203 * or PIT for the fast calibration to work.
204 *
205 * - with 256 PIT ticks to read the value, we have 214us to
206 * see the same MSB (and overhead like doing a single TSC
207 * read per MSB value etc).
208 *
209 * - We're doing 2 reads per loop (LSB, MSB), and we expect
210 * them each to take about a microsecond on real hardware.
211 * So we expect a count value of around 100. But we'll be
212 * generous, and accept anything over 50.
213 *
214 * - if the PIT is stuck, and we see *many* more reads, we
215 * return early (and the next caller of pit_expect_msb()
216 * then consider it a failure when they don't see the
217 * next expected value).
218 *
219 * These expectations mean that we know that we have seen the
220 * transition from one expected value to another with a fairly
221 * high accuracy, and we didn't miss any events. We can thus
222 * use the TSC value at the transitions to calculate a pretty
223 * good value for the TSC frequencty.
224 */
225static inline int pit_verify_msb(unsigned char val)
226{
227 /* Ignore LSB */
228 inb(0x42);
229 return inb(0x42) == val;
230}
231
232static inline int pit_expect_msb(unsigned char val, u64 *tscp,
233 unsigned long *deltap)
234{
235 int count;
236 u64 tsc = 0, prev_tsc = 0;
237
238 for (count = 0; count < 50000; count++) {
239 if (!pit_verify_msb(val))
240 break;
241 prev_tsc = tsc;
242 tsc = rdtsc();
243 }
244 *deltap = rdtsc() - prev_tsc;
245 *tscp = tsc;
246
247 /*
248 * We require _some_ success, but the quality control
249 * will be based on the error terms on the TSC values.
250 */
251 return count > 5;
252}
253
254/*
255 * How many MSB values do we want to see? We aim for
256 * a maximum error rate of 500ppm (in practice the
257 * real error is much smaller), but refuse to spend
258 * more than 50ms on it.
259 */
260#define MAX_QUICK_PIT_MS 50
261#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
262
Bin Mengb2eb48b2015-01-06 22:14:14 +0800263static unsigned long __maybe_unused quick_pit_calibrate(void)
Bin Mengbba97052014-11-09 22:19:25 +0800264{
265 int i;
266 u64 tsc, delta;
267 unsigned long d1, d2;
268
269 /* Set the Gate high, disable speaker */
270 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
271
272 /*
273 * Counter 2, mode 0 (one-shot), binary count
274 *
275 * NOTE! Mode 2 decrements by two (and then the
276 * output is flipped each time, giving the same
277 * final output frequency as a decrement-by-one),
278 * so mode 0 is much better when looking at the
279 * individual counts.
280 */
281 outb(0xb0, 0x43);
282
283 /* Start at 0xffff */
284 outb(0xff, 0x42);
285 outb(0xff, 0x42);
286
287 /*
288 * The PIT starts counting at the next edge, so we
289 * need to delay for a microsecond. The easiest way
290 * to do that is to just read back the 16-bit counter
291 * once from the PIT.
292 */
293 pit_verify_msb(0);
294
295 if (pit_expect_msb(0xff, &tsc, &d1)) {
296 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
297 if (!pit_expect_msb(0xff-i, &delta, &d2))
298 break;
299
300 /*
301 * Iterate until the error is less than 500 ppm
302 */
303 delta -= tsc;
304 if (d1+d2 >= delta >> 11)
305 continue;
306
307 /*
308 * Check the PIT one more time to verify that
309 * all TSC reads were stable wrt the PIT.
310 *
311 * This also guarantees serialization of the
312 * last cycle read ('d2') in pit_expect_msb.
313 */
314 if (!pit_verify_msb(0xfe - i))
315 break;
316 goto success;
317 }
318 }
319 debug("Fast TSC calibration failed\n");
320 return 0;
321
322success:
323 /*
324 * Ok, if we get here, then we've seen the
325 * MSB of the PIT decrement 'i' times, and the
326 * error has shrunk to less than 500 ppm.
327 *
328 * As a result, we can depend on there not being
329 * any odd delays anywhere, and the TSC reads are
330 * reliable (within the error).
331 *
332 * kHz = ticks / time-in-seconds / 1000;
333 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
334 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
335 */
336 delta *= PIT_TICK_RATE;
337 delta /= (i*256*1000);
338 debug("Fast TSC calibration using PIT\n");
339 return delta / 1000;
340}
341
Simon Glass11d7a5b2013-04-17 16:13:36 +0000342/* Get the speed of the TSC timer in MHz */
Bin Meng500361e2015-11-13 00:11:20 -0800343unsigned notrace long get_tbclk_mhz(void)
Simon Glass11d7a5b2013-04-17 16:13:36 +0000344{
Bin Meng976c2e82015-11-13 00:11:21 -0800345 return get_tbclk() / 1000000;
Simon Glass11d7a5b2013-04-17 16:13:36 +0000346}
347
Simon Glass11d7a5b2013-04-17 16:13:36 +0000348static ulong get_ms_timer(void)
349{
350 return (get_ticks() * 1000) / get_tbclk();
351}
352
353ulong get_timer(ulong base)
354{
355 return get_ms_timer() - base;
356}
357
Bin Meng500361e2015-11-13 00:11:20 -0800358ulong notrace timer_get_us(void)
Simon Glass11d7a5b2013-04-17 16:13:36 +0000359{
360 return get_ticks() / get_tbclk_mhz();
361}
362
363ulong timer_get_boot_us(void)
364{
365 return timer_get_us();
366}
367
368void __udelay(unsigned long usec)
369{
370 u64 now = get_ticks();
371 u64 stop;
372
373 stop = now + usec * get_tbclk_mhz();
374
375 while ((int64_t)(stop - get_ticks()) > 0)
Miao Yanb9f32772015-07-27 19:16:07 +0800376#if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
377 /*
378 * Add a 'pause' instruction on qemu target,
379 * to give other VCPUs a chance to run.
380 */
381 asm volatile("pause");
382#else
Simon Glass11d7a5b2013-04-17 16:13:36 +0000383 ;
Miao Yanb9f32772015-07-27 19:16:07 +0800384#endif
Simon Glass11d7a5b2013-04-17 16:13:36 +0000385}
386
Bin Meng976c2e82015-11-13 00:11:21 -0800387static int tsc_timer_get_count(struct udevice *dev, u64 *count)
388{
389 u64 now_tick = rdtsc();
390
391 *count = now_tick - gd->arch.tsc_base;
392
393 return 0;
394}
395
Bin Meng855e6572018-10-13 20:52:10 -0700396static void tsc_timer_ensure_setup(bool early)
Bin Meng976c2e82015-11-13 00:11:21 -0800397{
Simon Glassed10a4f2019-10-20 21:37:47 -0600398 if (gd->arch.tsc_inited)
Simon Glass471919d2017-09-05 19:49:46 -0600399 return;
Bin Meng976c2e82015-11-13 00:11:21 -0800400 gd->arch.tsc_base = rdtsc();
401
Simon Glass471919d2017-09-05 19:49:46 -0600402 if (!gd->arch.clock_rate) {
Bin Meng976c2e82015-11-13 00:11:21 -0800403 unsigned long fast_calibrate;
404
Bernhard Messerklinger0576f552019-01-07 12:14:40 +0100405 fast_calibrate = native_calibrate_tsc();
406 if (fast_calibrate)
407 goto done;
408
Christian Gmeiner1b1472a2018-05-14 11:32:17 +0200409 fast_calibrate = cpu_mhz_from_cpuid();
410 if (fast_calibrate)
411 goto done;
412
Bin Meng6ffad642017-07-25 20:12:05 -0700413 fast_calibrate = cpu_mhz_from_msr();
Christian Gmeiner1b1472a2018-05-14 11:32:17 +0200414 if (fast_calibrate)
415 goto done;
416
417 fast_calibrate = quick_pit_calibrate();
418 if (fast_calibrate)
419 goto done;
420
Bin Meng855e6572018-10-13 20:52:10 -0700421 if (early)
422 fast_calibrate = CONFIG_X86_TSC_TIMER_EARLY_FREQ;
Bin Meng20ffaae2018-08-10 02:39:36 -0700423 else
424 return;
Bin Meng976c2e82015-11-13 00:11:21 -0800425
Christian Gmeiner1b1472a2018-05-14 11:32:17 +0200426done:
Simon Glass471919d2017-09-05 19:49:46 -0600427 gd->arch.clock_rate = fast_calibrate * 1000000;
Bin Meng976c2e82015-11-13 00:11:21 -0800428 }
Simon Glassed10a4f2019-10-20 21:37:47 -0600429 gd->arch.tsc_inited = true;
Simon Glass471919d2017-09-05 19:49:46 -0600430}
431
432static int tsc_timer_probe(struct udevice *dev)
433{
434 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
435
Bin Meng20ffaae2018-08-10 02:39:36 -0700436 /* Try hardware calibration first */
437 tsc_timer_ensure_setup(false);
438 if (!gd->arch.clock_rate) {
439 /*
440 * Use the clock frequency specified in the
441 * device tree as last resort
442 */
443 if (!uc_priv->clock_rate)
444 panic("TSC frequency is ZERO");
Bin Meng1394fbb2018-06-23 03:03:47 -0700445 } else {
Bin Meng20ffaae2018-08-10 02:39:36 -0700446 uc_priv->clock_rate = gd->arch.clock_rate;
Bin Meng1394fbb2018-06-23 03:03:47 -0700447 }
Bin Meng976c2e82015-11-13 00:11:21 -0800448
449 return 0;
450}
451
Simon Glass471919d2017-09-05 19:49:46 -0600452unsigned long notrace timer_early_get_rate(void)
453{
Bin Meng1394fbb2018-06-23 03:03:47 -0700454 /*
455 * When TSC timer is used as the early timer, be warned that the timer
456 * clock rate can only be calibrated via some hardware ways. Specifying
457 * it in the device tree won't work for the early timer.
458 */
Bin Meng20ffaae2018-08-10 02:39:36 -0700459 tsc_timer_ensure_setup(true);
Simon Glass471919d2017-09-05 19:49:46 -0600460
461 return gd->arch.clock_rate;
462}
463
464u64 notrace timer_early_get_count(void)
465{
Simon Glass4a1050e2019-10-20 21:31:54 -0600466 tsc_timer_ensure_setup(true);
467
Simon Glass471919d2017-09-05 19:49:46 -0600468 return rdtsc() - gd->arch.tsc_base;
469}
470
Bin Meng976c2e82015-11-13 00:11:21 -0800471static const struct timer_ops tsc_timer_ops = {
472 .get_count = tsc_timer_get_count,
473};
474
475static const struct udevice_id tsc_timer_ids[] = {
476 { .compatible = "x86,tsc-timer", },
477 { }
478};
479
480U_BOOT_DRIVER(tsc_timer) = {
481 .name = "tsc_timer",
482 .id = UCLASS_TIMER,
483 .of_match = tsc_timer_ids,
484 .probe = tsc_timer_probe,
485 .ops = &tsc_timer_ops,
Bin Meng976c2e82015-11-13 00:11:21 -0800486};