Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 2 | /* |
Enric Balletbò i Serra | 19f9df8 | 2012-03-05 11:32:16 +0000 | [diff] [blame] | 3 | * Common configuration settings for IGEP technology based boards |
| 4 | * |
| 5 | * (C) Copyright 2012 |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 6 | * ISEE 2007 SL, <www.iseebcn.com> |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 7 | */ |
| 8 | |
Enric Balletbò i Serra | 19f9df8 | 2012-03-05 11:32:16 +0000 | [diff] [blame] | 9 | #ifndef __IGEP00X0_H |
| 10 | #define __IGEP00X0_H |
| 11 | |
Enric Balletbò i Serra | ed11648 | 2013-12-06 21:30:24 +0100 | [diff] [blame] | 12 | #include <configs/ti_omap3_common.h> |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 13 | |
Tom Rini | cfff4aa | 2016-08-26 13:30:43 -0400 | [diff] [blame] | 14 | /* |
| 15 | * We are only ever GP parts and will utilize all of the "downloaded image" |
| 16 | * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). |
| 17 | */ |
Enric Balletbo i Serra | 8aa10d4 | 2016-05-03 08:59:24 +0200 | [diff] [blame] | 18 | |
Pau Pajuelo | 4ddc309 | 2017-08-17 03:09:14 +0200 | [diff] [blame] | 19 | /* TPS65950 */ |
| 20 | #define PBIASLITEVMODE1 (1 << 8) |
| 21 | |
| 22 | /* LED */ |
| 23 | #define IGEP0020_GPIO_LED 27 |
| 24 | #define IGEP0030_GPIO_LED 16 |
| 25 | |
| 26 | /* Board and revision detection GPIOs */ |
| 27 | #define IGEP0030_USB_TRANSCEIVER_RESET 54 |
| 28 | #define GPIO_IGEP00X0_BOARD_DETECTION 28 |
| 29 | #define GPIO_IGEP00X0_REVISION_DETECTION 129 |
Javier Martinez Canillas | d549ace | 2012-12-27 03:36:01 +0000 | [diff] [blame] | 30 | |
Enric Balletbò i Serra | a5d75f7 | 2015-09-07 08:28:09 +0200 | [diff] [blame] | 31 | /* Environment */ |
| 32 | #define ENV_DEVICE_SETTINGS \ |
| 33 | "stdin=serial\0" \ |
| 34 | "stdout=serial\0" \ |
| 35 | "stderr=serial\0" |
| 36 | |
| 37 | #define MEM_LAYOUT_SETTINGS \ |
| 38 | DEFAULT_LINUX_BOOT_ENV \ |
| 39 | "scriptaddr=0x87E00000\0" \ |
| 40 | "pxefile_addr_r=0x87F00000\0" |
| 41 | |
| 42 | #define BOOT_TARGET_DEVICES(func) \ |
| 43 | func(MMC, mmc, 0) |
| 44 | |
| 45 | #include <config_distro_bootcmd.h> |
| 46 | |
Pau Pajuelo | 4ddc309 | 2017-08-17 03:09:14 +0200 | [diff] [blame] | 47 | #define ENV_FINDFDT \ |
| 48 | "findfdt="\ |
| 49 | "if test ${board_name} = igep0020; then " \ |
| 50 | "if test ${board_rev} = F; then " \ |
| 51 | "setenv fdtfile omap3-igep0020-rev-f.dtb; " \ |
| 52 | "else " \ |
| 53 | "setenv fdtfile omap3-igep0020.dtb; fi; fi; " \ |
| 54 | "if test ${board_name} = igep0030; then " \ |
| 55 | "if test ${board_rev} = G; then " \ |
| 56 | "setenv fdtfile omap3-igep0030-rev-g.dtb; " \ |
| 57 | "else " \ |
| 58 | "setenv fdtfile omap3-igep0030.dtb; fi; fi; " \ |
| 59 | "if test ${fdtfile} = ''; then " \ |
| 60 | "echo WARNING: Could not determine device tree to use; fi; \0" |
| 61 | |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 62 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Pau Pajuelo | 4ddc309 | 2017-08-17 03:09:14 +0200 | [diff] [blame] | 63 | ENV_FINDFDT \ |
Enric Balletbò i Serra | a5d75f7 | 2015-09-07 08:28:09 +0200 | [diff] [blame] | 64 | ENV_DEVICE_SETTINGS \ |
| 65 | MEM_LAYOUT_SETTINGS \ |
| 66 | BOOTENV |
Enric Balletbo i Serra | 4adf801 | 2011-04-19 09:16:36 -0400 | [diff] [blame] | 67 | |
Ladislav Michl | 43a6062 | 2016-07-12 20:28:32 +0200 | [diff] [blame] | 68 | /* OneNAND config */ |
Ladislav Michl | 43a6062 | 2016-07-12 20:28:32 +0200 | [diff] [blame] | 69 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP |
| 70 | #define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) |
Javier Martinez Canillas | 361fc83 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 71 | |
Ladislav Michl | 43a6062 | 2016-07-12 20:28:32 +0200 | [diff] [blame] | 72 | /* NAND config */ |
Ladislav Michl | 8ed5b0b | 2015-10-12 18:09:14 +0200 | [diff] [blame] | 73 | #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ |
| 74 | 10, 11, 12, 13, 14, 15, 16, 17, \ |
| 75 | 18, 19, 20, 21, 22, 23, 24, 25, \ |
| 76 | 26, 27, 28, 29, 30, 31, 32, 33, \ |
| 77 | 34, 35, 36, 37, 38, 39, 40, 41, \ |
| 78 | 42, 43, 44, 45, 46, 47, 48, 49, \ |
| 79 | 50, 51, 52, 53, 54, 55, 56, 57, } |
Javier Martinez Canillas | 361fc83 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 80 | #define CONFIG_SYS_NAND_ECCSIZE 512 |
Ladislav Michl | 8ed5b0b | 2015-10-12 18:09:14 +0200 | [diff] [blame] | 81 | #define CONFIG_SYS_NAND_ECCBYTES 14 |
Ladislav Michl | 8ed5b0b | 2015-10-12 18:09:14 +0200 | [diff] [blame] | 82 | |
Enric Balletbò i Serra | 19f9df8 | 2012-03-05 11:32:16 +0000 | [diff] [blame] | 83 | #endif /* __IGEP00X0_H */ |