blob: 3680c0fe442a2a5f9ca2cbc4553f895beadd298f [file] [log] [blame]
developer7305b4c2020-04-21 09:28:49 +02001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 *
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 */
7
8#ifndef __CONFIG_MT7628_H
9#define __CONFIG_MT7628_H
10
developer7305b4c2020-04-21 09:28:49 +020011#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
12
developer7305b4c2020-04-21 09:28:49 +020013#define CONFIG_SYS_SDRAM_BASE 0x80000000
developer7305b4c2020-04-21 09:28:49 +020014
15#define CONFIG_SYS_INIT_SP_OFFSET 0x80000
16
developer7305b4c2020-04-21 09:28:49 +020017/* Serial SPL */
Simon Glassf4d60392021-08-08 12:20:12 -060018#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
developer7305b4c2020-04-21 09:28:49 +020019#define CONFIG_SYS_NS16550_MEM32
20#define CONFIG_SYS_NS16550_CLK 40000000
21#define CONFIG_SYS_NS16550_REG_SIZE -4
22#define CONFIG_SYS_NS16550_COM1 0xb0000c00
developer7305b4c2020-04-21 09:28:49 +020023#endif
24
25/* Serial common */
26#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
27 230400, 460800, 921600 }
28
29/* SPL */
developer7305b4c2020-04-21 09:28:49 +020030
31#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
developer7305b4c2020-04-21 09:28:49 +020032
33/* Dummy value */
34#define CONFIG_SYS_UBOOT_BASE 0
35
36#endif /* __CONFIG_MT7628_H */