blob: 27c24228ef892ff88c8b08cc3e3a62e1538d5a70 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefano Babic771bfd12012-02-22 00:24:39 +00002/*
3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * Terry Lv <r65388@freescale.com>
Stefano Babic771bfd12012-02-22 00:24:39 +00005 */
6
Stefano Babic771bfd12012-02-22 00:24:39 +00007#include <ahci.h>
Simon Glass655306c2020-05-10 11:39:58 -06008#include <blk.h>
Jiaxun Yang0495a052024-05-17 19:14:53 +01009#include <clk.h>
Simon Glass63334482019-11-14 12:57:39 -070010#include <cpu_func.h>
Simon Glass0067b872017-07-29 11:35:16 -060011#include <dm.h>
12#include <dwc_ahsata.h>
Stefano Babic771bfd12012-02-22 00:24:39 +000013#include <fis.h>
Simon Glass602cedc2017-07-29 11:35:08 -060014#include <libata.h>
Simon Glass0f2af882020-05-10 11:40:05 -060015#include <log.h>
Stefano Babic771bfd12012-02-22 00:24:39 +000016#include <malloc.h>
Simon Glassf89b2502017-07-29 11:35:12 -060017#include <memalign.h>
Simon Glass655306c2020-05-10 11:39:58 -060018#include <part.h>
Simon Glass602cedc2017-07-29 11:35:08 -060019#include <sata.h>
Simon Glass274e0b02020-05-10 11:39:56 -060020#include <asm/cache.h>
Stefano Babic771bfd12012-02-22 00:24:39 +000021#include <asm/io.h>
Jiaxun Yang0495a052024-05-17 19:14:53 +010022#if IS_ENABLED(CONFIG_ARCH_MX5) || IS_ENABLED(CONFIG_ARCH_MX6)
Stefano Babic771bfd12012-02-22 00:24:39 +000023#include <asm/arch/clock.h>
Tim Harveye9d13472014-05-07 22:23:35 -070024#include <asm/arch/sys_proto.h>
Soeren Moch5569bbd2019-03-01 13:10:59 +010025#include <asm/mach-imx/sata.h>
Jiaxun Yang0495a052024-05-17 19:14:53 +010026#endif
Simon Glass602cedc2017-07-29 11:35:08 -060027#include <linux/bitops.h>
28#include <linux/ctype.h>
Simon Glassdbd79542020-05-10 11:40:11 -060029#include <linux/delay.h>
Simon Glass602cedc2017-07-29 11:35:08 -060030#include <linux/errno.h>
Simon Glass7b2a6292017-07-29 11:35:09 -060031#include "dwc_ahsata_priv.h"
Stefano Babic771bfd12012-02-22 00:24:39 +000032
33struct sata_port_regs {
34 u32 clb;
35 u32 clbu;
36 u32 fb;
37 u32 fbu;
38 u32 is;
39 u32 ie;
40 u32 cmd;
41 u32 res1[1];
42 u32 tfd;
43 u32 sig;
44 u32 ssts;
45 u32 sctl;
46 u32 serr;
47 u32 sact;
48 u32 ci;
49 u32 sntf;
50 u32 res2[1];
51 u32 dmacr;
52 u32 res3[1];
53 u32 phycr;
54 u32 physr;
55};
56
57struct sata_host_regs {
58 u32 cap;
59 u32 ghc;
60 u32 is;
61 u32 pi;
62 u32 vs;
63 u32 ccc_ctl;
64 u32 ccc_ports;
65 u32 res1[2];
66 u32 cap2;
67 u32 res2[30];
68 u32 bistafr;
69 u32 bistcr;
70 u32 bistfctr;
71 u32 bistsr;
72 u32 bistdecr;
73 u32 res3[2];
74 u32 oobr;
75 u32 res4[8];
76 u32 timer1ms;
77 u32 res5[1];
78 u32 gparam1r;
79 u32 gparam2r;
80 u32 pparamr;
81 u32 testr;
82 u32 versionr;
83 u32 idr;
84};
85
86#define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
87#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
88
89#define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
90
Tang Yuantian3f262d02015-07-09 14:37:30 +080091static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
Stefano Babic771bfd12012-02-22 00:24:39 +000092{
93 return base + 0x100 + (port * 0x80);
94}
95
96static int waiting_for_cmd_completed(u8 *offset,
97 int timeout_msec,
98 u32 sign)
99{
100 int i;
101 u32 status;
102
103 for (i = 0;
104 ((status = readl(offset)) & sign) && i < timeout_msec;
105 ++i)
106 mdelay(1);
107
108 return (i < timeout_msec) ? 0 : -1;
109}
110
Simon Glassb1f7f582017-07-29 11:35:04 -0600111static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk)
Stefano Babic771bfd12012-02-22 00:24:39 +0000112{
Simon Glassd30e76c2017-07-29 11:35:05 -0600113 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
Stefano Babic771bfd12012-02-22 00:24:39 +0000114
Simon Glass96f2af42017-07-29 11:35:07 -0600115 writel(SATA_HOST_OOBR_WE, &host_mmio->oobr);
116 writel(0x02060b14, &host_mmio->oobr);
Stefano Babic771bfd12012-02-22 00:24:39 +0000117
118 return 0;
119}
120
Jiaxun Yang0495a052024-05-17 19:14:53 +0100121static int ahci_host_init(struct ahci_uc_priv *uc_priv, int clk)
Stefano Babic771bfd12012-02-22 00:24:39 +0000122{
123 u32 tmp, cap_save, num_ports;
124 int i, j, timeout = 1000;
125 struct sata_port_regs *port_mmio = NULL;
Simon Glassd30e76c2017-07-29 11:35:05 -0600126 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
Stefano Babic771bfd12012-02-22 00:24:39 +0000127
Simon Glass96f2af42017-07-29 11:35:07 -0600128 cap_save = readl(&host_mmio->cap);
Stefano Babic771bfd12012-02-22 00:24:39 +0000129 cap_save |= SATA_HOST_CAP_SSS;
130
131 /* global controller reset */
Simon Glass96f2af42017-07-29 11:35:07 -0600132 tmp = readl(&host_mmio->ghc);
Stefano Babic771bfd12012-02-22 00:24:39 +0000133 if ((tmp & SATA_HOST_GHC_HR) == 0)
Simon Glass96f2af42017-07-29 11:35:07 -0600134 writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc);
Stefano Babic771bfd12012-02-22 00:24:39 +0000135
Simon Glass96f2af42017-07-29 11:35:07 -0600136 while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout)
Stefano Babic771bfd12012-02-22 00:24:39 +0000137 ;
138
139 if (timeout <= 0) {
140 debug("controller reset failed (0x%x)\n", tmp);
141 return -1;
142 }
143
144 /* Set timer 1ms */
Simon Glass96f2af42017-07-29 11:35:07 -0600145 writel(clk / 1000, &host_mmio->timer1ms);
Stefano Babic771bfd12012-02-22 00:24:39 +0000146
Simon Glassb1f7f582017-07-29 11:35:04 -0600147 ahci_setup_oobr(uc_priv, 0);
Stefano Babic771bfd12012-02-22 00:24:39 +0000148
Simon Glass96f2af42017-07-29 11:35:07 -0600149 writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc);
150 writel(cap_save, &host_mmio->cap);
Stefano Babic771bfd12012-02-22 00:24:39 +0000151 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
Simon Glass96f2af42017-07-29 11:35:07 -0600152 writel_with_flush((1 << num_ports) - 1, &host_mmio->pi);
Stefano Babic771bfd12012-02-22 00:24:39 +0000153
154 /*
155 * Determine which Ports are implemented by the DWC_ahsata,
156 * by reading the PI register. This bit map value aids the
157 * software to determine how many Ports are available and
158 * which Port registers need to be initialized.
159 */
Simon Glass96f2af42017-07-29 11:35:07 -0600160 uc_priv->cap = readl(&host_mmio->cap);
161 uc_priv->port_map = readl(&host_mmio->pi);
Stefano Babic771bfd12012-02-22 00:24:39 +0000162
163 /* Determine how many command slots the HBA supports */
Simon Glassb1f7f582017-07-29 11:35:04 -0600164 uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1;
Stefano Babic771bfd12012-02-22 00:24:39 +0000165
166 debug("cap 0x%x port_map 0x%x n_ports %d\n",
Simon Glassb1f7f582017-07-29 11:35:04 -0600167 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
Stefano Babic771bfd12012-02-22 00:24:39 +0000168
Simon Glassb1f7f582017-07-29 11:35:04 -0600169 for (i = 0; i < uc_priv->n_ports; i++) {
170 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i);
Simon Glassd30e76c2017-07-29 11:35:05 -0600171 port_mmio = uc_priv->port[i].port_mmio;
Stefano Babic771bfd12012-02-22 00:24:39 +0000172
173 /* Ensure that the DWC_ahsata is in idle state */
Simon Glass96f2af42017-07-29 11:35:07 -0600174 tmp = readl(&port_mmio->cmd);
Stefano Babic771bfd12012-02-22 00:24:39 +0000175
176 /*
177 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
178 * are all cleared, the Port is in an idle state.
179 */
180 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
181 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
182
183 /*
184 * System software places a Port into the idle state by
185 * clearing P#CMD.ST and waiting for P#CMD.CR to return
186 * 0 when read.
187 */
188 tmp &= ~SATA_PORT_CMD_ST;
Simon Glass96f2af42017-07-29 11:35:07 -0600189 writel_with_flush(tmp, &port_mmio->cmd);
Stefano Babic771bfd12012-02-22 00:24:39 +0000190
191 /*
192 * spec says 500 msecs for each bit, so
193 * this is slightly incorrect.
194 */
195 mdelay(500);
196
197 timeout = 1000;
Simon Glass96f2af42017-07-29 11:35:07 -0600198 while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR)
Stefano Babic771bfd12012-02-22 00:24:39 +0000199 && --timeout)
200 ;
201
202 if (timeout <= 0) {
203 debug("port reset failed (0x%x)\n", tmp);
204 return -1;
205 }
206 }
207
208 /* Spin-up device */
Simon Glass96f2af42017-07-29 11:35:07 -0600209 tmp = readl(&port_mmio->cmd);
210 writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd);
Stefano Babic771bfd12012-02-22 00:24:39 +0000211
212 /* Wait for spin-up to finish */
213 timeout = 1000;
Simon Glass96f2af42017-07-29 11:35:07 -0600214 while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD)
Stefano Babic771bfd12012-02-22 00:24:39 +0000215 && --timeout)
216 ;
217 if (timeout <= 0) {
218 debug("Spin-Up can't finish!\n");
219 return -1;
220 }
221
222 for (j = 0; j < 100; ++j) {
223 mdelay(10);
Simon Glass96f2af42017-07-29 11:35:07 -0600224 tmp = readl(&port_mmio->ssts);
Stefano Babic771bfd12012-02-22 00:24:39 +0000225 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
226 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
227 break;
228 }
229
230 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
231 timeout = 1000;
Ye Lif1c562e2020-05-03 22:27:01 +0800232 while (!(readl(&port_mmio->serr) & SATA_PORT_SERR_DIAG_X)
Stefano Babic771bfd12012-02-22 00:24:39 +0000233 && --timeout)
234 ;
235 if (timeout <= 0) {
236 debug("Can't find DIAG_X set!\n");
237 return -1;
238 }
239
240 /*
241 * For each implemented Port, clear the P#SERR
242 * register, by writing ones to each implemented\
243 * bit location.
244 */
Simon Glass96f2af42017-07-29 11:35:07 -0600245 tmp = readl(&port_mmio->serr);
Stefano Babic771bfd12012-02-22 00:24:39 +0000246 debug("P#SERR 0x%x\n",
247 tmp);
Simon Glass96f2af42017-07-29 11:35:07 -0600248 writel(tmp, &port_mmio->serr);
Stefano Babic771bfd12012-02-22 00:24:39 +0000249
250 /* Ack any pending irq events for this port */
Simon Glass96f2af42017-07-29 11:35:07 -0600251 tmp = readl(&host_mmio->is);
Stefano Babic771bfd12012-02-22 00:24:39 +0000252 debug("IS 0x%x\n", tmp);
253 if (tmp)
Simon Glass96f2af42017-07-29 11:35:07 -0600254 writel(tmp, &host_mmio->is);
Stefano Babic771bfd12012-02-22 00:24:39 +0000255
Simon Glass96f2af42017-07-29 11:35:07 -0600256 writel(1 << i, &host_mmio->is);
Stefano Babic771bfd12012-02-22 00:24:39 +0000257
258 /* set irq mask (enables interrupts) */
Simon Glass96f2af42017-07-29 11:35:07 -0600259 writel(DEF_PORT_IRQ, &port_mmio->ie);
Stefano Babic771bfd12012-02-22 00:24:39 +0000260
261 /* register linkup ports */
Simon Glass96f2af42017-07-29 11:35:07 -0600262 tmp = readl(&port_mmio->ssts);
Stefano Babic771bfd12012-02-22 00:24:39 +0000263 debug("Port %d status: 0x%x\n", i, tmp);
264 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
Simon Glassb1f7f582017-07-29 11:35:04 -0600265 uc_priv->link_port_map |= (0x01 << i);
Stefano Babic771bfd12012-02-22 00:24:39 +0000266 }
267
Simon Glass96f2af42017-07-29 11:35:07 -0600268 tmp = readl(&host_mmio->ghc);
Stefano Babic771bfd12012-02-22 00:24:39 +0000269 debug("GHC 0x%x\n", tmp);
Simon Glass96f2af42017-07-29 11:35:07 -0600270 writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc);
271 tmp = readl(&host_mmio->ghc);
Stefano Babic771bfd12012-02-22 00:24:39 +0000272 debug("GHC 0x%x\n", tmp);
273
274 return 0;
275}
276
Simon Glassb1f7f582017-07-29 11:35:04 -0600277static void ahci_print_info(struct ahci_uc_priv *uc_priv)
Stefano Babic771bfd12012-02-22 00:24:39 +0000278{
Simon Glassd30e76c2017-07-29 11:35:05 -0600279 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
Stefano Babic771bfd12012-02-22 00:24:39 +0000280 u32 vers, cap, impl, speed;
281 const char *speed_s;
282 const char *scc_s;
283
Simon Glass96f2af42017-07-29 11:35:07 -0600284 vers = readl(&host_mmio->vs);
Simon Glassb1f7f582017-07-29 11:35:04 -0600285 cap = uc_priv->cap;
286 impl = uc_priv->port_map;
Stefano Babic771bfd12012-02-22 00:24:39 +0000287
288 speed = (cap & SATA_HOST_CAP_ISS_MASK)
289 >> SATA_HOST_CAP_ISS_OFFSET;
290 if (speed == 1)
291 speed_s = "1.5";
292 else if (speed == 2)
293 speed_s = "3";
294 else
295 speed_s = "?";
296
297 scc_s = "SATA";
298
299 printf("AHCI %02x%02x.%02x%02x "
300 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
301 (vers >> 24) & 0xff,
302 (vers >> 16) & 0xff,
303 (vers >> 8) & 0xff,
304 vers & 0xff,
305 ((cap >> 8) & 0x1f) + 1,
306 (cap & 0x1f) + 1,
307 speed_s,
308 impl,
309 scc_s);
310
311 printf("flags: "
312 "%s%s%s%s%s%s"
313 "%s%s%s%s%s%s%s\n",
314 cap & (1 << 31) ? "64bit " : "",
315 cap & (1 << 30) ? "ncq " : "",
316 cap & (1 << 28) ? "ilck " : "",
317 cap & (1 << 27) ? "stag " : "",
318 cap & (1 << 26) ? "pm " : "",
319 cap & (1 << 25) ? "led " : "",
320 cap & (1 << 24) ? "clo " : "",
321 cap & (1 << 19) ? "nz " : "",
322 cap & (1 << 18) ? "only " : "",
323 cap & (1 << 17) ? "pmp " : "",
324 cap & (1 << 15) ? "pio " : "",
325 cap & (1 << 14) ? "slum " : "",
326 cap & (1 << 13) ? "part " : "");
327}
328
Simon Glassb1f7f582017-07-29 11:35:04 -0600329static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
330 unsigned char *buf, int buf_len)
Stefano Babic771bfd12012-02-22 00:24:39 +0000331{
Simon Glass96f2af42017-07-29 11:35:07 -0600332 struct ahci_ioports *pp = &uc_priv->port[port];
Stefano Babic771bfd12012-02-22 00:24:39 +0000333 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
Jiaxun Yangaf5fd392024-05-17 19:14:52 +0100334 phys_addr_t pa = virt_to_phys(buf);
Stefano Babic771bfd12012-02-22 00:24:39 +0000335 u32 sg_count, max_bytes;
336 int i;
337
338 max_bytes = MAX_DATA_BYTES_PER_SG;
339 sg_count = ((buf_len - 1) / max_bytes) + 1;
340 if (sg_count > AHCI_MAX_SG) {
341 printf("Error:Too much sg!\n");
342 return -1;
343 }
344
345 for (i = 0; i < sg_count; i++) {
Jiaxun Yangaf5fd392024-05-17 19:14:52 +0100346 ahci_sg->addr = cpu_to_le32(lower_32_bits(pa));
347 ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa));
Stefano Babic771bfd12012-02-22 00:24:39 +0000348 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
349 (buf_len < max_bytes
350 ? (buf_len - 1)
351 : (max_bytes - 1)));
352 ahci_sg++;
353 buf_len -= max_bytes;
354 }
355
356 return sg_count;
357}
358
359static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
360{
361 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
362 AHCI_CMD_SLOT_SZ * cmd_slot);
Jiaxun Yangaf5fd392024-05-17 19:14:52 +0100363 phys_addr_t pa = virt_to_phys(pp->cmd_tbl);
Stefano Babic771bfd12012-02-22 00:24:39 +0000364
365 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
366 cmd_hdr->opts = cpu_to_le32(opts);
367 cmd_hdr->status = 0;
Jiaxun Yangaf5fd392024-05-17 19:14:52 +0100368 pp->cmd_slot->tbl_addr = cpu_to_le32(lower_32_bits(pa));
Tang Yuantian3f262d02015-07-09 14:37:30 +0800369#ifdef CONFIG_PHYS_64BIT
Jiaxun Yangaf5fd392024-05-17 19:14:52 +0100370 pp->cmd_slot->tbl_addr_hi = cpu_to_le32(upper_32_bits(pa));
Tang Yuantian3f262d02015-07-09 14:37:30 +0800371#endif
Stefano Babic771bfd12012-02-22 00:24:39 +0000372}
373
374#define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
375
Simon Glassb1f7f582017-07-29 11:35:04 -0600376static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
377 struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len,
378 s32 is_write)
Stefano Babic771bfd12012-02-22 00:24:39 +0000379{
Simon Glass96f2af42017-07-29 11:35:07 -0600380 struct ahci_ioports *pp = &uc_priv->port[port];
Simon Glassd30e76c2017-07-29 11:35:05 -0600381 struct sata_port_regs *port_mmio = pp->port_mmio;
Stefano Babic771bfd12012-02-22 00:24:39 +0000382 u32 opts;
383 int sg_count = 0, cmd_slot = 0;
384
Simon Glass96f2af42017-07-29 11:35:07 -0600385 cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci));
Stefano Babic771bfd12012-02-22 00:24:39 +0000386 if (32 == cmd_slot) {
387 printf("Can't find empty command slot!\n");
388 return 0;
389 }
390
391 /* Check xfer length */
392 if (buf_len > MAX_BYTES_PER_TRANS) {
393 printf("Max transfer length is %dB\n\r",
394 MAX_BYTES_PER_TRANS);
395 return 0;
396 }
397
398 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
399 if (buf && buf_len)
Simon Glassb1f7f582017-07-29 11:35:04 -0600400 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
Stefano Babic771bfd12012-02-22 00:24:39 +0000401 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
Eric Nelson998816b2013-06-15 16:09:55 -0700402 if (is_write) {
Stefano Babic771bfd12012-02-22 00:24:39 +0000403 opts |= 0x40;
Eric Nelson998816b2013-06-15 16:09:55 -0700404 flush_cache((ulong)buf, buf_len);
405 }
Stefano Babic771bfd12012-02-22 00:24:39 +0000406 ahci_fill_cmd_slot(pp, cmd_slot, opts);
407
Jiaxun Yangaf5fd392024-05-17 19:14:52 +0100408 flush_cache((ulong)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
Simon Glass96f2af42017-07-29 11:35:07 -0600409 writel_with_flush(1 << cmd_slot, &port_mmio->ci);
Stefano Babic771bfd12012-02-22 00:24:39 +0000410
Simon Glass96f2af42017-07-29 11:35:07 -0600411 if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000,
412 0x1 << cmd_slot)) {
Stefano Babic771bfd12012-02-22 00:24:39 +0000413 printf("timeout exit!\n");
414 return -1;
415 }
Jiaxun Yangaf5fd392024-05-17 19:14:52 +0100416 invalidate_dcache_range((ulong)(pp->cmd_slot),
417 (ulong)(pp->cmd_slot) + AHCI_PORT_PRIV_DMA_SZ);
Stefano Babic771bfd12012-02-22 00:24:39 +0000418 debug("ahci_exec_ata_cmd: %d byte transferred.\n",
419 pp->cmd_slot->status);
Eric Nelson998816b2013-06-15 16:09:55 -0700420 if (!is_write)
421 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
Stefano Babic771bfd12012-02-22 00:24:39 +0000422
423 return buf_len;
424}
425
Simon Glassc5fc2a32017-07-29 11:35:06 -0600426static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port)
Stefano Babic771bfd12012-02-22 00:24:39 +0000427{
Eric Nelson998816b2013-06-15 16:09:55 -0700428 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
429 struct sata_fis_h2d *cfis = &h2d;
Stefano Babic771bfd12012-02-22 00:24:39 +0000430
431 memset(cfis, 0, sizeof(struct sata_fis_h2d));
432 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
433 cfis->pm_port_c = 1 << 7;
434 cfis->command = ATA_CMD_SET_FEATURES;
435 cfis->features = SETFEATURES_XFER;
Simon Glassb1f7f582017-07-29 11:35:04 -0600436 cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e;
Stefano Babic771bfd12012-02-22 00:24:39 +0000437
Simon Glassb1f7f582017-07-29 11:35:04 -0600438 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD);
Stefano Babic771bfd12012-02-22 00:24:39 +0000439}
440
Simon Glassb1f7f582017-07-29 11:35:04 -0600441static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
Stefano Babic771bfd12012-02-22 00:24:39 +0000442{
Simon Glass96f2af42017-07-29 11:35:07 -0600443 struct ahci_ioports *pp = &uc_priv->port[port];
Simon Glassd30e76c2017-07-29 11:35:05 -0600444 struct sata_port_regs *port_mmio = pp->port_mmio;
Jiaxun Yangaf5fd392024-05-17 19:14:52 +0100445 phys_addr_t dma_addr;
Stefano Babic771bfd12012-02-22 00:24:39 +0000446 u32 port_status;
Jiaxun Yangaf5fd392024-05-17 19:14:52 +0100447 void *mem;
Stefano Babic771bfd12012-02-22 00:24:39 +0000448 int timeout = 10000000;
449
450 debug("Enter start port: %d\n", port);
Simon Glass96f2af42017-07-29 11:35:07 -0600451 port_status = readl(&port_mmio->ssts);
Stefano Babic771bfd12012-02-22 00:24:39 +0000452 debug("Port %d status: %x\n", port, port_status);
453 if ((port_status & 0xf) != 0x03) {
454 printf("No Link on this port!\n");
455 return -1;
456 }
457
Jiaxun Yangaf5fd392024-05-17 19:14:52 +0100458 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
Stefano Babic771bfd12012-02-22 00:24:39 +0000459 if (!mem) {
Stefano Babic771bfd12012-02-22 00:24:39 +0000460 printf("No mem for table!\n");
461 return -ENOMEM;
462 }
463
Jiaxun Yangaf5fd392024-05-17 19:14:52 +0100464 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
Stefano Babic771bfd12012-02-22 00:24:39 +0000465
466 /*
467 * First item in chunk of DMA memory: 32-slot command table,
468 * 32 bytes each in size
469 */
470 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
Jiaxun Yangaf5fd392024-05-17 19:14:52 +0100471 mem += AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT;
Stefano Babic771bfd12012-02-22 00:24:39 +0000472
473 /*
474 * Second item: Received-FIS area, 256-Byte aligned
475 */
476 pp->rx_fis = mem;
477 mem += AHCI_RX_FIS_SZ;
478
479 /*
480 * Third item: data area for storing a single command
481 * and its scatter-gather table
482 */
483 pp->cmd_tbl = mem;
Stefano Babic771bfd12012-02-22 00:24:39 +0000484 mem += AHCI_CMD_TBL_HDR;
Jiaxun Yangaf5fd392024-05-17 19:14:52 +0100485 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
Stefano Babic771bfd12012-02-22 00:24:39 +0000486
Simon Glass96f2af42017-07-29 11:35:07 -0600487 writel_with_flush(0x00004444, &port_mmio->dmacr);
Jiaxun Yangaf5fd392024-05-17 19:14:52 +0100488 dma_addr = virt_to_phys(pp->cmd_slot);
489 debug("cmd_slot_dma = 0x%08llx\n", (u64)dma_addr);
490 writel_with_flush(lower_32_bits(dma_addr), &port_mmio->clb);
491 writel_with_flush(upper_32_bits(dma_addr), &port_mmio->clbu);
492 dma_addr = virt_to_phys(pp->cmd_slot);
493 debug("rx_fis_slot_dma = 0x%08llx\n", (u64)dma_addr);
494 writel_with_flush(lower_32_bits(dma_addr), &port_mmio->fb);
495 writel_with_flush(upper_32_bits(dma_addr), &port_mmio->fbu);
496
Stefano Babic771bfd12012-02-22 00:24:39 +0000497
498 /* Enable FRE */
Simon Glass96f2af42017-07-29 11:35:07 -0600499 writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)),
500 &port_mmio->cmd);
Stefano Babic771bfd12012-02-22 00:24:39 +0000501
502 /* Wait device ready */
Simon Glass96f2af42017-07-29 11:35:07 -0600503 while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR |
Stefano Babic771bfd12012-02-22 00:24:39 +0000504 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
505 && --timeout)
506 ;
507 if (timeout <= 0) {
508 debug("Device not ready for BSY, DRQ and"
509 "ERR in TFD!\n");
510 return -1;
511 }
512
513 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
514 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
Simon Glass96f2af42017-07-29 11:35:07 -0600515 PORT_CMD_START, &port_mmio->cmd);
Stefano Babic771bfd12012-02-22 00:24:39 +0000516
517 debug("Exit start port %d\n", port);
518
519 return 0;
520}
521
Simon Glassc5fc2a32017-07-29 11:35:06 -0600522static void dwc_ahsata_print_info(struct blk_desc *pdev)
Stefano Babic771bfd12012-02-22 00:24:39 +0000523{
Stefano Babic771bfd12012-02-22 00:24:39 +0000524 printf("SATA Device Info:\n\r");
Stefano Babic771bfd12012-02-22 00:24:39 +0000525 printf("S/N: %s\n\rProduct model number: %s\n\r"
Soeren Moch71657f12019-03-01 13:10:58 +0100526 "Firmware version: %s\n\rCapacity: " LBAFU " sectors\n\r",
Stefano Babic771bfd12012-02-22 00:24:39 +0000527 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
Stefano Babic771bfd12012-02-22 00:24:39 +0000528}
529
Simon Glassc5fc2a32017-07-29 11:35:06 -0600530static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
Stefano Babic771bfd12012-02-22 00:24:39 +0000531{
Eric Nelson998816b2013-06-15 16:09:55 -0700532 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
533 struct sata_fis_h2d *cfis = &h2d;
Simon Glassb1f7f582017-07-29 11:35:04 -0600534 u8 port = uc_priv->hard_port_no;
Stefano Babic771bfd12012-02-22 00:24:39 +0000535
536 memset(cfis, 0, sizeof(struct sata_fis_h2d));
537
538 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
539 cfis->pm_port_c = 0x80; /* is command */
540 cfis->command = ATA_CMD_ID_ATA;
541
Simon Glassb1f7f582017-07-29 11:35:04 -0600542 ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2,
543 READ_CMD);
Stefano Babic771bfd12012-02-22 00:24:39 +0000544 ata_swap_buf_le16(id, ATA_ID_WORDS);
545}
546
Simon Glassc5fc2a32017-07-29 11:35:06 -0600547static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id)
Stefano Babic771bfd12012-02-22 00:24:39 +0000548{
Simon Glassb1f7f582017-07-29 11:35:04 -0600549 uc_priv->pio_mask = id[ATA_ID_PIO_MODES];
550 uc_priv->udma_mask = id[ATA_ID_UDMA_MODES];
551 debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask);
Stefano Babic771bfd12012-02-22 00:24:39 +0000552}
553
Simon Glassc5fc2a32017-07-29 11:35:06 -0600554static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start,
555 u32 blkcnt, u8 *buffer, int is_write)
Stefano Babic771bfd12012-02-22 00:24:39 +0000556{
Eric Nelson998816b2013-06-15 16:09:55 -0700557 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
558 struct sata_fis_h2d *cfis = &h2d;
Simon Glassb1f7f582017-07-29 11:35:04 -0600559 u8 port = uc_priv->hard_port_no;
Stefano Babic771bfd12012-02-22 00:24:39 +0000560 u32 block;
561
562 block = start;
563
564 memset(cfis, 0, sizeof(struct sata_fis_h2d));
565
566 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
567 cfis->pm_port_c = 0x80; /* is command */
568 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
569 cfis->device = ATA_LBA;
570
571 cfis->device |= (block >> 24) & 0xf;
572 cfis->lba_high = (block >> 16) & 0xff;
573 cfis->lba_mid = (block >> 8) & 0xff;
574 cfis->lba_low = block & 0xff;
575 cfis->sector_count = (u8)(blkcnt & 0xff);
576
Simon Glassb1f7f582017-07-29 11:35:04 -0600577 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
578 ATA_SECT_SIZE * blkcnt, is_write) > 0)
Stefano Babic771bfd12012-02-22 00:24:39 +0000579 return blkcnt;
580 else
581 return 0;
582}
583
Simon Glassc5fc2a32017-07-29 11:35:06 -0600584static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv)
Stefano Babic771bfd12012-02-22 00:24:39 +0000585{
Eric Nelson998816b2013-06-15 16:09:55 -0700586 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
587 struct sata_fis_h2d *cfis = &h2d;
Simon Glassb1f7f582017-07-29 11:35:04 -0600588 u8 port = uc_priv->hard_port_no;
Stefano Babic771bfd12012-02-22 00:24:39 +0000589
590 memset(cfis, 0, sizeof(struct sata_fis_h2d));
591
592 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
593 cfis->pm_port_c = 0x80; /* is command */
594 cfis->command = ATA_CMD_FLUSH;
595
Simon Glassb1f7f582017-07-29 11:35:04 -0600596 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
Stefano Babic771bfd12012-02-22 00:24:39 +0000597}
598
Simon Glassc5fc2a32017-07-29 11:35:06 -0600599static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start,
600 lbaint_t blkcnt, u8 *buffer, int is_write)
Stefano Babic771bfd12012-02-22 00:24:39 +0000601{
Eric Nelson998816b2013-06-15 16:09:55 -0700602 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
603 struct sata_fis_h2d *cfis = &h2d;
Simon Glassb1f7f582017-07-29 11:35:04 -0600604 u8 port = uc_priv->hard_port_no;
Stefano Babic771bfd12012-02-22 00:24:39 +0000605 u64 block;
606
607 block = (u64)start;
608
609 memset(cfis, 0, sizeof(struct sata_fis_h2d));
610
611 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
612 cfis->pm_port_c = 0x80; /* is command */
613
614 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
615 : ATA_CMD_READ_EXT;
616
617 cfis->lba_high_exp = (block >> 40) & 0xff;
618 cfis->lba_mid_exp = (block >> 32) & 0xff;
619 cfis->lba_low_exp = (block >> 24) & 0xff;
620 cfis->lba_high = (block >> 16) & 0xff;
621 cfis->lba_mid = (block >> 8) & 0xff;
622 cfis->lba_low = block & 0xff;
623 cfis->device = ATA_LBA;
624 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
625 cfis->sector_count = blkcnt & 0xff;
626
Simon Glassb1f7f582017-07-29 11:35:04 -0600627 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
628 ATA_SECT_SIZE * blkcnt, is_write) > 0)
Stefano Babic771bfd12012-02-22 00:24:39 +0000629 return blkcnt;
630 else
631 return 0;
632}
633
Simon Glassc5fc2a32017-07-29 11:35:06 -0600634static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv)
Stefano Babic771bfd12012-02-22 00:24:39 +0000635{
Eric Nelson998816b2013-06-15 16:09:55 -0700636 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
637 struct sata_fis_h2d *cfis = &h2d;
Simon Glassb1f7f582017-07-29 11:35:04 -0600638 u8 port = uc_priv->hard_port_no;
Stefano Babic771bfd12012-02-22 00:24:39 +0000639
640 memset(cfis, 0, sizeof(struct sata_fis_h2d));
641
642 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
643 cfis->pm_port_c = 0x80; /* is command */
644 cfis->command = ATA_CMD_FLUSH_EXT;
645
Simon Glassb1f7f582017-07-29 11:35:04 -0600646 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
Stefano Babic771bfd12012-02-22 00:24:39 +0000647}
648
Simon Glassc5fc2a32017-07-29 11:35:06 -0600649static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id)
Stefano Babic771bfd12012-02-22 00:24:39 +0000650{
Stefano Babic771bfd12012-02-22 00:24:39 +0000651 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
Simon Glassb1f7f582017-07-29 11:35:04 -0600652 uc_priv->flags |= SATA_FLAG_WCACHE;
Stefano Babic771bfd12012-02-22 00:24:39 +0000653 if (ata_id_has_flush(id))
Simon Glassb1f7f582017-07-29 11:35:04 -0600654 uc_priv->flags |= SATA_FLAG_FLUSH;
Stefano Babic771bfd12012-02-22 00:24:39 +0000655 if (ata_id_has_flush_ext(id))
Simon Glassb1f7f582017-07-29 11:35:04 -0600656 uc_priv->flags |= SATA_FLAG_FLUSH_EXT;
Stefano Babic771bfd12012-02-22 00:24:39 +0000657}
658
Simon Glassc5fc2a32017-07-29 11:35:06 -0600659static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr,
660 lbaint_t blkcnt, const void *buffer,
661 int is_write)
Stefano Babic771bfd12012-02-22 00:24:39 +0000662{
663 u32 start, blks;
664 u8 *addr;
665 int max_blks;
666
667 start = blknr;
668 blks = blkcnt;
669 addr = (u8 *)buffer;
670
671 max_blks = ATA_MAX_SECTORS_LBA48;
672
673 do {
674 if (blks > max_blks) {
Simon Glassc5fc2a32017-07-29 11:35:06 -0600675 if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start,
676 max_blks, addr,
677 is_write))
Stefano Babic771bfd12012-02-22 00:24:39 +0000678 return 0;
679 start += max_blks;
680 blks -= max_blks;
681 addr += ATA_SECT_SIZE * max_blks;
682 } else {
Simon Glassc5fc2a32017-07-29 11:35:06 -0600683 if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks,
684 addr, is_write))
Stefano Babic771bfd12012-02-22 00:24:39 +0000685 return 0;
686 start += blks;
687 blks = 0;
688 addr += ATA_SECT_SIZE * blks;
689 }
690 } while (blks != 0);
691
692 return blkcnt;
693}
694
Simon Glassc5fc2a32017-07-29 11:35:06 -0600695static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr,
696 lbaint_t blkcnt, const void *buffer,
697 int is_write)
Stefano Babic771bfd12012-02-22 00:24:39 +0000698{
699 u32 start, blks;
700 u8 *addr;
701 int max_blks;
702
703 start = blknr;
704 blks = blkcnt;
705 addr = (u8 *)buffer;
706
707 max_blks = ATA_MAX_SECTORS;
708 do {
709 if (blks > max_blks) {
Simon Glassc5fc2a32017-07-29 11:35:06 -0600710 if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start,
711 max_blks, addr,
712 is_write))
Stefano Babic771bfd12012-02-22 00:24:39 +0000713 return 0;
714 start += max_blks;
715 blks -= max_blks;
716 addr += ATA_SECT_SIZE * max_blks;
717 } else {
Simon Glassc5fc2a32017-07-29 11:35:06 -0600718 if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks,
719 addr, is_write))
Stefano Babic771bfd12012-02-22 00:24:39 +0000720 return 0;
721 start += blks;
722 blks = 0;
723 addr += ATA_SECT_SIZE * blks;
724 }
725 } while (blks != 0);
726
727 return blkcnt;
728}
729
Simon Glassf89b2502017-07-29 11:35:12 -0600730static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv)
731{
732 u32 linkmap;
733 int i;
734
735 linkmap = uc_priv->link_port_map;
736
737 if (0 == linkmap) {
738 printf("No port device detected!\n");
739 return -ENXIO;
740 }
741
742 for (i = 0; i < uc_priv->n_ports; i++) {
743 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
744 if (ahci_port_start(uc_priv, (u8)i)) {
745 printf("Can not start port %d\n", i);
746 return 1;
747 }
748 uc_priv->hard_port_no = i;
749 break;
750 }
751 }
752
753 return 0;
754}
755
756static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv,
757 struct blk_desc *pdev)
758{
759 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
760 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
761 u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
Simon Glassf89b2502017-07-29 11:35:12 -0600762 u8 port = uc_priv->hard_port_no;
763 ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS);
764
765 /* Identify device to get information */
766 dwc_ahsata_identify(uc_priv, id);
767
768 /* Serial number */
769 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
770 memcpy(pdev->product, serial, sizeof(serial));
771
772 /* Firmware version */
773 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
774 memcpy(pdev->revision, firmware, sizeof(firmware));
775
776 /* Product model */
777 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
778 memcpy(pdev->vendor, product, sizeof(product));
779
Soeren Moch71657f12019-03-01 13:10:58 +0100780 /* Total sectors */
781 pdev->lba = ata_id_n_sectors(id);
Simon Glassf89b2502017-07-29 11:35:12 -0600782
783 pdev->type = DEV_TYPE_HARDDISK;
784 pdev->blksz = ATA_SECT_SIZE;
785 pdev->lun = 0;
786
787 /* Check if support LBA48 */
788 if (ata_id_has_lba48(id)) {
789 pdev->lba48 = 1;
790 debug("Device support LBA48\n\r");
791 }
792
793 /* Get the NCQ queue depth from device */
794 uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
795 uc_priv->flags |= ata_id_queue_depth(id);
796
797 /* Get the xfer mode from device */
798 dwc_ahsata_xfer_mode(uc_priv, id);
799
800 /* Get the write cache status from device */
801 dwc_ahsata_init_wcache(uc_priv, id);
802
803 /* Set the xfer mode to highest speed */
804 ahci_set_feature(uc_priv, port);
805
806 dwc_ahsata_print_info(pdev);
807
808 return 0;
809}
810
811/*
812 * SATA interface between low level driver and command layer
813 */
814static ulong sata_read_common(struct ahci_uc_priv *uc_priv,
815 struct blk_desc *desc, ulong blknr,
816 lbaint_t blkcnt, void *buffer)
817{
818 u32 rc;
819
820 if (desc->lba48)
821 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
822 READ_CMD);
823 else
824 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
825 READ_CMD);
826
827 return rc;
828}
829
830static ulong sata_write_common(struct ahci_uc_priv *uc_priv,
831 struct blk_desc *desc, ulong blknr,
832 lbaint_t blkcnt, const void *buffer)
833{
834 u32 rc;
835 u32 flags = uc_priv->flags;
836
837 if (desc->lba48) {
838 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
839 WRITE_CMD);
840 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT))
841 dwc_ahsata_flush_cache_ext(uc_priv);
842 } else {
843 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
844 WRITE_CMD);
845 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH))
846 dwc_ahsata_flush_cache(uc_priv);
847 }
848
849 return rc;
850}
851
Simon Glass0067b872017-07-29 11:35:16 -0600852int dwc_ahsata_port_status(struct udevice *dev, int port)
853{
854 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
855 struct sata_port_regs *port_mmio;
856
857 port_mmio = uc_priv->port[port].port_mmio;
858 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK ? 0 : -ENXIO;
859}
860
861int dwc_ahsata_bus_reset(struct udevice *dev)
862{
863 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
864 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
865
866 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
867 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
868 udelay(100);
869
870 return 0;
871}
872
873int dwc_ahsata_scan(struct udevice *dev)
874{
875 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
876 struct blk_desc *desc;
877 struct udevice *blk;
878 int ret;
879
880 /*
881 * Create only one block device and do detection
882 * to make sure that there won't be a lot of
883 * block devices created
884 */
885 device_find_first_child(dev, &blk);
886 if (!blk) {
887 ret = blk_create_devicef(dev, "dwc_ahsata_blk", "blk",
Bin Meng2294ecb2023-09-26 16:43:31 +0800888 UCLASS_AHCI, -1, DEFAULT_BLKSZ,
889 0, &blk);
Simon Glass0067b872017-07-29 11:35:16 -0600890 if (ret) {
891 debug("Can't create device\n");
892 return ret;
893 }
894 }
895
Simon Glass71fa5b42020-12-03 16:55:18 -0700896 desc = dev_get_uclass_plat(blk);
Simon Glass0067b872017-07-29 11:35:16 -0600897 ret = dwc_ahsata_scan_common(uc_priv, desc);
898 if (ret) {
899 debug("%s: Failed to scan bus\n", __func__);
900 return ret;
901 }
902
AKASHI Takahiro927a7a52022-03-08 20:36:43 +0900903 ret = blk_probe_or_unbind(dev);
904 if (ret < 0)
905 /* TODO: undo create */
906 return ret;
907
Simon Glass0067b872017-07-29 11:35:16 -0600908 return 0;
909}
910
911int dwc_ahsata_probe(struct udevice *dev)
912{
913 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
Jiaxun Yang0495a052024-05-17 19:14:53 +0100914 struct clk_bulk clk_bulk __maybe_unused;
915 struct clk clk __maybe_unused;
916 int sataclk;
Simon Glass0067b872017-07-29 11:35:16 -0600917 int ret;
918
Jiaxun Yang0495a052024-05-17 19:14:53 +0100919#if IS_ENABLED(CONFIG_MX6)
Soeren Moch5569bbd2019-03-01 13:10:59 +0100920 setup_sata();
921#endif
Jiaxun Yang0495a052024-05-17 19:14:53 +0100922#if IS_ENABLED(CONFIG_MX5) || IS_ENABLED(CONFIG_MX6)
923 sataclk = mxc_get_clock(MXC_SATA_CLK);
924#else
925 ret = clk_get_bulk(dev, &clk_bulk);
926 if (ret)
927 return ret;
928
929 ret = clk_enable_bulk(&clk_bulk);
930 if (ret)
931 return ret;
932
933 ret = clk_get_by_name(dev, "sata", &clk);
934 if (ret)
935 return ret;
936
937 sataclk = clk_get_rate(&clk);
938#endif
939 if (IS_ERR_VALUE(sataclk)) {
940 log_err("Unable to get SATA clock rate\n");
941 return -EINVAL;
942 }
Simon Glass0067b872017-07-29 11:35:16 -0600943 uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
944 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
Johan Jonker8d5d8e02023-03-13 01:32:04 +0100945 uc_priv->mmio_base = dev_read_addr_ptr(dev);
Simon Glass0067b872017-07-29 11:35:16 -0600946
947 /* initialize adapter */
Jiaxun Yang0495a052024-05-17 19:14:53 +0100948 ret = ahci_host_init(uc_priv, sataclk);
Simon Glass0067b872017-07-29 11:35:16 -0600949 if (ret)
950 return ret;
951
952 ahci_print_info(uc_priv);
953
954 return dwc_ahci_start_ports(uc_priv);
955}
956
957static ulong dwc_ahsata_read(struct udevice *blk, lbaint_t blknr,
958 lbaint_t blkcnt, void *buffer)
959{
Simon Glass71fa5b42020-12-03 16:55:18 -0700960 struct blk_desc *desc = dev_get_uclass_plat(blk);
Simon Glass0067b872017-07-29 11:35:16 -0600961 struct udevice *dev = dev_get_parent(blk);
962 struct ahci_uc_priv *uc_priv;
963
964 uc_priv = dev_get_uclass_priv(dev);
965 return sata_read_common(uc_priv, desc, blknr, blkcnt, buffer);
966}
967
968static ulong dwc_ahsata_write(struct udevice *blk, lbaint_t blknr,
969 lbaint_t blkcnt, const void *buffer)
970{
Simon Glass71fa5b42020-12-03 16:55:18 -0700971 struct blk_desc *desc = dev_get_uclass_plat(blk);
Simon Glass0067b872017-07-29 11:35:16 -0600972 struct udevice *dev = dev_get_parent(blk);
973 struct ahci_uc_priv *uc_priv;
974
975 uc_priv = dev_get_uclass_priv(dev);
976 return sata_write_common(uc_priv, desc, blknr, blkcnt, buffer);
977}
978
979static const struct blk_ops dwc_ahsata_blk_ops = {
980 .read = dwc_ahsata_read,
981 .write = dwc_ahsata_write,
982};
983
984U_BOOT_DRIVER(dwc_ahsata_blk) = {
985 .name = "dwc_ahsata_blk",
986 .id = UCLASS_BLK,
987 .ops = &dwc_ahsata_blk_ops,
988};
989
Soeren Moch5569bbd2019-03-01 13:10:59 +0100990struct ahci_ops dwc_ahsata_ahci_ops = {
991 .port_status = dwc_ahsata_port_status,
992 .reset = dwc_ahsata_bus_reset,
993 .scan = dwc_ahsata_scan,
994};
995
996static const struct udevice_id dwc_ahsata_ahci_ids[] = {
Jiaxun Yang0495a052024-05-17 19:14:53 +0100997 { .compatible = "fsl,imx53-ahci" },
Soeren Moch5569bbd2019-03-01 13:10:59 +0100998 { .compatible = "fsl,imx6q-ahci" },
Jiaxun Yang0495a052024-05-17 19:14:53 +0100999 { .compatible = "fsl,imx6qp-ahci" },
Soeren Moch5569bbd2019-03-01 13:10:59 +01001000 { }
1001};
1002
1003U_BOOT_DRIVER(dwc_ahsata_ahci) = {
1004 .name = "dwc_ahsata_ahci",
1005 .id = UCLASS_AHCI,
1006 .of_match = dwc_ahsata_ahci_ids,
1007 .ops = &dwc_ahsata_ahci_ops,
1008 .probe = dwc_ahsata_probe,
1009};