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Masahiro Yamada408dd772016-03-18 16:41:51 +09001/*
2 * UniPhier SC (System Control) block registers for ARMv8 SoCs
3 *
Masahiro Yamadad11b0b72016-09-17 03:33:11 +09004 * Copyright (C) 2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada408dd772016-03-18 16:41:51 +09006 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef SC64_REGS_H
11#define SC64_REGS_H
12
13#define SC_BASE_ADDR 0x61840000
14
Masahiro Yamada408dd772016-03-18 16:41:51 +090015#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
16#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
17#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
Masahiro Yamada408dd772016-03-18 16:41:51 +090018#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010)
19#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014)
20#define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018)
Masahiro Yamada408dd772016-03-18 16:41:51 +090021
22#define SC_CLKCTRL (SC_BASE_ADDR | 0x2100)
23#define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108)
24#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
Masahiro Yamada408dd772016-03-18 16:41:51 +090025#define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110)
26#define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114)
27#define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118)
Masahiro Yamada408dd772016-03-18 16:41:51 +090028
Masahiro Yamada3cdbc1a2016-10-12 21:14:38 +090029#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000)
30#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004)
31#define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8008)
Masahiro Yamada090785d2016-09-22 07:42:19 +090032#define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080)
33#define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084)
34#define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088)
35#define SC_CA_GEARUPD (1 << 0)
36
Masahiro Yamada408dd772016-03-18 16:41:51 +090037#endif /* SC64_REGS_H */