| commit | 090785d8cebada5ac57c920c4808fb047523f20a | [log] [tgz] |
|---|---|---|
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | Thu Sep 22 07:42:19 2016 +0900 |
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | Fri Sep 23 01:00:23 2016 +0900 |
| tree | 4a31e92876cb55753ac16aac95fb2dbe57236b3d | |
| parent | 8bcd0ec971f8344545541a6415d731989da98125 [diff] |
ARM: uniphier: add PLL init code for LD11 SoC - Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set the Cortex-A53 clock to the maximum frequency since it is running at 500MHz (SPLL/4) on startup Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>