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git01.mediatek.com / filogic / uboot / 034d8ff5c20a2899cb960eeda131fd9c1ccabd1d / . / arch / arm / cpu / pxa / start.S
blob: ab7bcb4e56256eab7709303d00072f38784a6263 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]2/*
Marek Vasutb9091622011-10-31 14:12:39 +0100[diff] [blame]3 * armboot - Startup Code for XScale CPU-core
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]4 *
5 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
6 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
7 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
wdenkc0aa5c52003-12-06 19:49:23 +0000[diff] [blame]8 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
Marek Vasutb9091622011-10-31 14:12:39 +0100[diff] [blame]9 * Copyright (C) 2001 Marius Groger <mag@sysgo.de>
10 * Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
11 * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
wdenk1fe2c702003-03-06 21:55:29 +0000[diff] [blame]12 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
Wolfgang Denk61ccd1d2006-03-06 23:18:48 +0100[diff] [blame]13 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
Marek Vasutb9091622011-10-31 14:12:39 +0100[diff] [blame]14 * Copyright (C) 2003 Kshitij <kshitij@ti.com>
15 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
16 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
17 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
18 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]19 */
20
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]21#include <asm-offsets.h>
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]22#include <config.h>
Marek Vasutf1ac7842011-11-05 19:26:47 +0100[diff] [blame]23
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]24/*
Marek Vasutb9091622011-10-31 14:12:39 +0100[diff] [blame]25 *************************************************************************
26 *
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]27 * Startup Code (reset vector)
28 *
Marek Vasutb9091622011-10-31 14:12:39 +0100[diff] [blame]29 * do important init only if we don't start from memory!
30 * setup Memory and board specific bits prior to relocation.
31 * relocate armboot to ram
32 * setup stack
33 *
34 *************************************************************************
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]35 */
36
Albert ARIBAUD9852cc62014-04-15 16:13:51 +0200[diff] [blame]37 .globl reset
Heiko Schocher3d8f5fa2010-09-17 13:10:46 +0200[diff] [blame]38
39reset:
40 /*
41 * set the cpu to SVC32 mode
42 */
43 mrs r0,cpsr
44 bic r0,r0,#0x1f
45 orr r0,r0,#0xd3
46 msr cpsr,r0
47
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]48#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
Marek Vasutb9091622011-10-31 14:12:39 +0100[diff] [blame]49 bl cpu_init_crit
50#endif
Heiko Schocher3d8f5fa2010-09-17 13:10:46 +0200[diff] [blame]51
Vasily Khoruzhick3b5ab622016-03-20 18:37:06 -0700[diff] [blame]52#ifdef CONFIG_CPU_PXA27X
53 /*
54 * enable clock for SRAM
55 */
56 ldr r0,=CKEN
57 ldr r1,[r0]
58 orr r1,r1,#(1 << 20)
59 str r1,[r0]
60#endif
Albert ARIBAUDfacdae52013-01-08 10:18:02 +0000[diff] [blame]61 bl _main
Heiko Schocher3d8f5fa2010-09-17 13:10:46 +0200[diff] [blame]62
63/*------------------------------------------------------------------------------*/
Heiko Schocher3d8f5fa2010-09-17 13:10:46 +0200[diff] [blame]64
Albert ARIBAUD9580b322013-05-19 01:48:15 +0000[diff] [blame]65 .globl c_runtime_cpu_setup
66c_runtime_cpu_setup:
Albert ARIBAUDfacdae52013-01-08 10:18:02 +0000[diff] [blame]67 bx lr
Albert ARIBAUDfacdae52013-01-08 10:18:02 +0000[diff] [blame]68
Marek Vasutb9091622011-10-31 14:12:39 +0100[diff] [blame]69/*
70 *************************************************************************
71 *
72 * CPU_init_critical registers
73 *
74 * setup important registers
75 * setup memory timing
76 *
77 *************************************************************************
78 */
Tom Rini56bf6a82022-05-25 16:13:48 -0400[diff] [blame]79#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
Marek Vasutb9091622011-10-31 14:12:39 +0100[diff] [blame]80cpu_init_crit:
81 /*
82 * flush v4 I/D caches
83 */
84 mov r0, #0
85 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
86 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
Markus Klotzbücherd5dfcf92006-02-28 23:11:07 +0100[diff] [blame]87
Marek Vasutb9091622011-10-31 14:12:39 +0100[diff] [blame]88 /*
89 * disable MMU stuff and caches
90 */
91 mrc p15, 0, r0, c1, c0, 0
Mike Dunncfe695c2013-06-17 10:47:28 -0700[diff] [blame]92 bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS)
Marek Vasutb9091622011-10-31 14:12:39 +0100[diff] [blame]93 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
Yuichiro Goto8d4b7e92016-02-25 10:23:34 +0900[diff] [blame]94 orr r0, r0, #0x00000002 @ set bit 1 (A) Align
Marek Vasutb9091622011-10-31 14:12:39 +0100[diff] [blame]95 mcr p15, 0, r0, c1, c0, 0
wdenk1fe2c702003-03-06 21:55:29 +0000[diff] [blame]96
Marek Vasutb9091622011-10-31 14:12:39 +0100[diff] [blame]97 mov pc, lr /* back to my caller */
Tom Rini56bf6a82022-05-25 16:13:48 -0400[diff] [blame]98#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */