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git01.mediatek.com / filogic / uboot / c609719b8d1b2dca590e0ed499016d041203e403 / . / cpu / xscale / start.S
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wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame^]1/*
2 * armboot - Startup Code for XScale
3 *
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Kyle Harris <kharris@nexus-tech.net>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29
30
31#include <config.h>
32#include <version.h>
33
34.globl _start
35_start: b reset
36 ldr pc, _undefined_instruction
37 ldr pc, _software_interrupt
38 ldr pc, _prefetch_abort
39 ldr pc, _data_abort
40 ldr pc, _not_used
41 ldr pc, _irq
42 ldr pc, _fiq
43
44_undefined_instruction: .word undefined_instruction
45_software_interrupt: .word software_interrupt
46_prefetch_abort: .word prefetch_abort
47_data_abort: .word data_abort
48_not_used: .word not_used
49_irq: .word irq
50_fiq: .word fiq
51
52 .balignl 16,0xdeadbeef
53
54
55/*
56 * Startup Code (reset vector)
57 *
58 * do important init only if we don't start from memory!
59 * - relocate armboot to ram
60 * - setup stack
61 * - jump to second stage
62 */
63
64/*
65 * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
66 */
67_TEXT_BASE:
68 .word TEXT_BASE
69
70.globl _armboot_start
71_armboot_start:
72 .word _start
73
74/*
75 * Note: _armboot_end_data and _armboot_end are defined
76 * by the (board-dependent) linker script.
77 * _armboot_end_data is the first usable FLASH address after armboot
78 */
79.globl _armboot_end_data
80_armboot_end_data:
81 .word armboot_end_data
82.globl _armboot_end
83_armboot_end:
84 .word armboot_end
85
86/*
87 * _armboot_real_end is the first usable RAM address behind armboot
88 * and the various stacks
89 */
90.globl _armboot_real_end
91_armboot_real_end:
92 .word 0x0badc0de
93
94/*
95 * We relocate uboot to this address (end of RAM - 128 KiB)
96 */
97.globl _uboot_reloc
98_uboot_reloc:
99 .word CFG_DRAM_BASE + CFG_DRAM_SIZE - CFG_MONITOR_LEN
100
101#ifdef CONFIG_USE_IRQ
102/* IRQ stack memory (calculated at run-time) */
103.globl IRQ_STACK_START
104IRQ_STACK_START:
105 .word 0x0badc0de
106
107/* IRQ stack memory (calculated at run-time) */
108.globl FIQ_STACK_START
109FIQ_STACK_START:
110 .word 0x0badc0de
111#endif
112
113
114/****************************************************************************/
115/* */
116/* the actual reset code */
117/* */
118/****************************************************************************/
119
120reset:
121 mrs r0,cpsr /* set the cpu to SVC32 mode */
122 bic r0,r0,#0x1f /* (superviser mode, M=10011) */
123 orr r0,r0,#0x13
124 msr cpsr,r0
125
126 bl cpu_init_crit /* we do sys-critical inits */
127
128relocate: /* relocate U-Boot to RAM */
129 adr r0, _start /* r0 <- current position of code */
130 ldr r2, _armboot_start
131 ldr r3, _armboot_end
132 sub r2, r3, r2 /* r2 <- size of armboot */
133/* ldr r1, _uboot_reloc / * r1 <- destination address */
134 ldr r1, _TEXT_BASE
135 add r2, r0, r2 /* r2 <- source end address */
136
137copy_loop:
138 ldmia r0!, {r3-r10} /* copy from source address [r0] */
139 stmia r1!, {r3-r10} /* copy to target address [r1] */
140 cmp r0, r2 /* until source end addreee [r2] */
141 ble copy_loop
142
143 /* Set up the stack */
144 ldr r0, _uboot_reloc /* upper 128 KiB: relocated uboot */
145 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
146 /* FIXME: bdinfo should be here */
147 sub sp, r0, #12 /* leave 3 words for abort-stack */
148
149 ldr pc, _start_armboot
150
151_start_armboot: .word start_armboot
152
153
154/****************************************************************************/
155/* */
156/* CPU_init_critical registers */
157/* */
158/* - setup important registers */
159/* - setup memory timing */
160/* */
161/****************************************************************************/
162
163 /* Interrupt-Controller base address */
164IC_BASE: .word 0x40d00000
165#define ICMR 0x04
166
167/* Reset-Controller */
168RST_BASE: .word 0x40f00030
169#define RCSR 0x00
170
171
172 /* Clock Manager Registers */
173CC_BASE: .word 0x41300000
174#define CCCR 0x00
175cpuspeed: .word CFG_CPUSPEED
176
177 /* RS: ??? */
178 .macro CPWAIT
179 mrc p15,0,r0,c2,c0,0
180 mov r0,r0
181 sub pc,pc,#4
182 .endm
183
184
185cpu_init_crit:
186
187 /* mask all IRQs */
188 ldr r0, IC_BASE
189 mov r1, #0x00
190 str r1, [r0, #ICMR]
191
192 /* set clock speed */
193 ldr r0, CC_BASE
194 ldr r1, cpuspeed
195 str r1, [r0, #CCCR]
196
197 /*
198 * before relocating, we have to setup RAM timing
199 * because memory timing is board-dependend, you will
200 * find a memsetup.S in your board directory.
201 */
202 mov ip, lr
203 bl memsetup
204 mov lr, ip
205
206 /* Memory interfaces are working. Disable MMU and enable I-cache. */
207
208 ldr r0, =0x2001 /* enable access to all coproc. */
209 mcr p15, 0, r0, c15, c1, 0
210 CPWAIT
211
212 mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
213 CPWAIT
214
215 mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
216 CPWAIT
217
218 mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
219 CPWAIT
220
221 /* Enable the Icache */
222/*
223 mrc p15, 0, r0, c1, c0, 0
224 orr r0, r0, #0x1800
225 mcr p15, 0, r0, c1, c0, 0
226 CPWAIT
227*/
228 mov pc, lr
229
230
231/****************************************************************************/
232/* */
233/* Interrupt handling */
234/* */
235/****************************************************************************/
236
237/* IRQ stack frame */
238
239#define S_FRAME_SIZE 72
240
241#define S_OLD_R0 68
242#define S_PSR 64
243#define S_PC 60
244#define S_LR 56
245#define S_SP 52
246
247#define S_IP 48
248#define S_FP 44
249#define S_R10 40
250#define S_R9 36
251#define S_R8 32
252#define S_R7 28
253#define S_R6 24
254#define S_R5 20
255#define S_R4 16
256#define S_R3 12
257#define S_R2 8
258#define S_R1 4
259#define S_R0 0
260
261#define MODE_SVC 0x13
262
263 /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
264
265 .macro bad_save_user_regs
266 sub sp, sp, #S_FRAME_SIZE
267 stmia sp, {r0 - r12} /* Calling r0-r12 */
268 add r8, sp, #S_PC
269
270 ldr r2, _armboot_end
271 add r2, r2, #CONFIG_STACKSIZE
272 sub r2, r2, #8
273 ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
274 add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
275
276 add r5, sp, #S_SP
277 mov r1, lr
278 stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
279 mov r0, sp
280 .endm
281
282
283 /* use irq_save_user_regs / irq_restore_user_regs for */
284 /* IRQ/FIQ handling */
285
286 .macro irq_save_user_regs
287 sub sp, sp, #S_FRAME_SIZE
288 stmia sp, {r0 - r12} /* Calling r0-r12 */
289 add r8, sp, #S_PC
290 stmdb r8, {sp, lr}^ /* Calling SP, LR */
291 str lr, [r8, #0] /* Save calling PC */
292 mrs r6, spsr
293 str r6, [r8, #4] /* Save CPSR */
294 str r0, [r8, #8] /* Save OLD_R0 */
295 mov r0, sp
296 .endm
297
298 .macro irq_restore_user_regs
299 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
300 mov r0, r0
301 ldr lr, [sp, #S_PC] @ Get PC
302 add sp, sp, #S_FRAME_SIZE
303 subs pc, lr, #4 @ return & move spsr_svc into cpsr
304 .endm
305
306 .macro get_bad_stack
307 ldr r13, _armboot_end @ setup our mode stack
308 add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
309 sub r13, r13, #8
310
311 str lr, [r13] @ save caller lr / spsr
312 mrs lr, spsr
313 str lr, [r13, #4]
314
315 mov r13, #MODE_SVC @ prepare SVC-Mode
316 msr spsr_c, r13
317 mov lr, pc
318 movs pc, lr
319 .endm
320
321 .macro get_irq_stack @ setup IRQ stack
322 ldr sp, IRQ_STACK_START
323 .endm
324
325 .macro get_fiq_stack @ setup FIQ stack
326 ldr sp, FIQ_STACK_START
327 .endm
328
329
330/****************************************************************************/
331/* */
332/* exception handlers */
333/* */
334/****************************************************************************/
335
336 .align 5
337undefined_instruction:
338 get_bad_stack
339 bad_save_user_regs
340 bl do_undefined_instruction
341
342 .align 5
343software_interrupt:
344 get_bad_stack
345 bad_save_user_regs
346 bl do_software_interrupt
347
348 .align 5
349prefetch_abort:
350 get_bad_stack
351 bad_save_user_regs
352 bl do_prefetch_abort
353
354 .align 5
355data_abort:
356 get_bad_stack
357 bad_save_user_regs
358 bl do_data_abort
359
360 .align 5
361not_used:
362 get_bad_stack
363 bad_save_user_regs
364 bl do_not_used
365
366#ifdef CONFIG_USE_IRQ
367
368 .align 5
369irq:
370 get_irq_stack
371 irq_save_user_regs
372 bl do_irq
373 irq_restore_user_regs
374
375 .align 5
376fiq:
377 get_fiq_stack
378 irq_save_user_regs /* someone ought to write a more */
379 bl do_fiq /* effiction fiq_save_user_regs */
380 irq_restore_user_regs
381
382#else
383
384 .align 5
385irq:
386 get_bad_stack
387 bad_save_user_regs
388 bl do_irq
389
390 .align 5
391fiq:
392 get_bad_stack
393 bad_save_user_regs
394 bl do_fiq
395
396#endif
397
398/*
399 * FIXME How do we reset??? Watchdog timeout??
400 */
401 .align 5
402.globl reset_cpu
403reset_cpu:
404 /*
405 ldr r0, RST_BASE
406 mov r1, #0x0 @ set bit 3-0 ...
407 str r1, [r0, #RCSR] @ ... to clear in RCSR
408 mov r1, #0x1
409 str r1, [r0, #RCSR] @ and perform reset
410 */
411 b reset_cpu @ silly, but repeat endlessly
412