blob: b213a942fde40062c6b8cc58ed4372de80c03f9a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glassfc0ba2d2015-01-01 16:18:15 -07002/*
3 * (C) Copyright 2014 Google, Inc
Simon Glassfc0ba2d2015-01-01 16:18:15 -07004 */
5
6#include <common.h>
Simon Glassed38aef2020-05-10 11:40:03 -06007#include <command.h>
Simon Glass7403c262020-07-17 08:48:22 -06008#include <log.h>
Simon Glassfc0ba2d2015-01-01 16:18:15 -07009#include <asm/msr.h>
Simon Glass7403c262020-07-17 08:48:22 -060010#include <asm/mp.h>
Simon Glassfc0ba2d2015-01-01 16:18:15 -070011#include <asm/mtrr.h>
12
13static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
14 "Uncacheable",
15 "Combine",
16 "2",
17 "3",
18 "Through",
19 "Protect",
20 "Back",
21};
22
Simon Glass7403c262020-07-17 08:48:22 -060023static void read_mtrrs(void *arg)
Simon Glassfc0ba2d2015-01-01 16:18:15 -070024{
Simon Glass7403c262020-07-17 08:48:22 -060025 struct mtrr_info *info = arg;
26
27 mtrr_read_all(info);
28}
29
Simon Glassfbf120c2020-09-22 14:54:51 -060030static int do_mtrr_list(int reg_count, int cpu_select)
Simon Glass7403c262020-07-17 08:48:22 -060031{
32 struct mtrr_info info;
33 int ret;
Simon Glassfc0ba2d2015-01-01 16:18:15 -070034 int i;
35
36 printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||",
37 "Mask ||", "Size ||");
Simon Glass7403c262020-07-17 08:48:22 -060038 memset(&info, '\0', sizeof(info));
39 ret = mp_run_on_cpus(cpu_select, read_mtrrs, &info);
40 if (ret)
41 return log_msg_ret("run", ret);
Simon Glassfbf120c2020-09-22 14:54:51 -060042 for (i = 0; i < reg_count; i++) {
Simon Glassfc0ba2d2015-01-01 16:18:15 -070043 const char *type = "Invalid";
44 uint64_t base, mask, size;
45 bool valid;
46
Simon Glass7403c262020-07-17 08:48:22 -060047 base = info.mtrr[i].base;
48 mask = info.mtrr[i].mask;
Simon Glassfc0ba2d2015-01-01 16:18:15 -070049 size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1);
50 size |= (1 << 12) - 1;
51 size += 1;
52 valid = mask & MTRR_PHYS_MASK_VALID;
53 type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK];
54 printf("%d %-5s %-12s %016llx %016llx %016llx\n", i,
Bin Meng933a29b2015-07-06 16:31:32 +080055 valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK,
56 mask & ~MTRR_PHYS_MASK_VALID, size);
Simon Glassfc0ba2d2015-01-01 16:18:15 -070057 }
58
59 return 0;
60}
61
Simon Glass29e1d772020-07-17 08:48:27 -060062static int do_mtrr_set(int cpu_select, uint reg, int argc, char *const argv[])
Simon Glassfc0ba2d2015-01-01 16:18:15 -070063{
64 const char *typename = argv[0];
Simon Glassfc0ba2d2015-01-01 16:18:15 -070065 uint32_t start, size;
66 uint64_t base, mask;
67 int i, type = -1;
68 bool valid;
Simon Glass29e1d772020-07-17 08:48:27 -060069 int ret;
Simon Glassfc0ba2d2015-01-01 16:18:15 -070070
71 if (argc < 3)
72 return CMD_RET_USAGE;
73 for (i = 0; i < MTRR_TYPE_COUNT; i++) {
74 if (*typename == *mtrr_type_name[i])
75 type = i;
76 }
77 if (type == -1) {
78 printf("Invalid type name %s\n", typename);
79 return CMD_RET_USAGE;
80 }
Simon Glass3ff49ec2021-07-24 09:03:29 -060081 start = hextoul(argv[1], NULL);
82 size = hextoul(argv[2], NULL);
Simon Glassfc0ba2d2015-01-01 16:18:15 -070083
84 base = start | type;
85 valid = native_read_msr(MTRR_PHYS_MASK_MSR(reg)) & MTRR_PHYS_MASK_VALID;
86 mask = ~((uint64_t)size - 1);
87 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
88 if (valid)
89 mask |= MTRR_PHYS_MASK_VALID;
90
Simon Glass29e1d772020-07-17 08:48:27 -060091 ret = mtrr_set(cpu_select, reg, base, mask);
92 if (ret)
93 return CMD_RET_FAILURE;
Simon Glassfc0ba2d2015-01-01 16:18:15 -070094
95 return 0;
96}
97
Simon Glassed38aef2020-05-10 11:40:03 -060098static int do_mtrr(struct cmd_tbl *cmdtp, int flag, int argc,
99 char *const argv[])
Simon Glassfc0ba2d2015-01-01 16:18:15 -0700100{
Simon Glassfbf120c2020-09-22 14:54:51 -0600101 int reg_count = mtrr_get_var_count();
Simon Glass2c601b62020-07-17 08:48:28 -0600102 int cmd;
Simon Glass7403c262020-07-17 08:48:22 -0600103 int cpu_select;
Simon Glassfc0ba2d2015-01-01 16:18:15 -0700104 uint reg;
Simon Glass2c601b62020-07-17 08:48:28 -0600105 int ret;
Simon Glassfc0ba2d2015-01-01 16:18:15 -0700106
Simon Glass7403c262020-07-17 08:48:22 -0600107 cpu_select = MP_SELECT_BSP;
Simon Glasse643edd2020-07-17 08:48:29 -0600108 if (argc >= 3 && !strcmp("-c", argv[1])) {
109 const char *cpustr;
110
111 cpustr = argv[2];
112 if (*cpustr == 'a')
113 cpu_select = MP_SELECT_ALL;
114 else
115 cpu_select = simple_strtol(cpustr, NULL, 16);
116 argc -= 2;
117 argv += 2;
118 }
Simon Glass2c601b62020-07-17 08:48:28 -0600119 argc--;
120 argv++;
121 cmd = argv[0] ? *argv[0] : 0;
122 if (argc < 1 || !cmd) {
123 cmd = 'l';
124 reg = 0;
Wolfgang Wallner9abf45b2020-08-14 09:55:24 +0200125 }
126 if (cmd != 'l') {
Simon Glass2c601b62020-07-17 08:48:28 -0600127 if (argc < 2)
128 return CMD_RET_USAGE;
Simon Glass3ff49ec2021-07-24 09:03:29 -0600129 reg = hextoul(argv[1], NULL);
Simon Glassfbf120c2020-09-22 14:54:51 -0600130 if (reg >= reg_count) {
Simon Glass2c601b62020-07-17 08:48:28 -0600131 printf("Invalid register number\n");
132 return CMD_RET_USAGE;
133 }
134 }
135 if (cmd == 'l') {
Simon Glass3ac9fdb2020-07-17 08:48:31 -0600136 bool first;
137 int i;
138
139 i = mp_first_cpu(cpu_select);
140 if (i < 0) {
141 printf("Invalid CPU (err=%d)\n", i);
142 return CMD_RET_FAILURE;
143 }
144 first = true;
145 for (; i >= 0; i = mp_next_cpu(cpu_select, i)) {
146 if (!first)
147 printf("\n");
148 printf("CPU %d:\n", i);
Simon Glassfbf120c2020-09-22 14:54:51 -0600149 ret = do_mtrr_list(reg_count, i);
Simon Glass3ac9fdb2020-07-17 08:48:31 -0600150 if (ret) {
151 printf("Failed to read CPU %d (err=%d)\n", i,
152 ret);
153 return CMD_RET_FAILURE;
154 }
155 first = false;
156 }
Simon Glass2c601b62020-07-17 08:48:28 -0600157 } else {
158 switch (cmd) {
159 case 'e':
160 ret = mtrr_set_valid(cpu_select, reg, true);
161 break;
162 case 'd':
163 ret = mtrr_set_valid(cpu_select, reg, false);
164 break;
165 case 's':
166 ret = do_mtrr_set(cpu_select, reg, argc - 2, argv + 2);
167 break;
168 default:
169 return CMD_RET_USAGE;
170 }
171 if (ret) {
172 printf("Operation failed (err=%d)\n", ret);
173 return CMD_RET_FAILURE;
174 }
Simon Glassfc0ba2d2015-01-01 16:18:15 -0700175 }
Simon Glassfc0ba2d2015-01-01 16:18:15 -0700176
177 return 0;
178}
179
180U_BOOT_CMD(
Simon Glasse643edd2020-07-17 08:48:29 -0600181 mtrr, 8, 1, do_mtrr,
Simon Glassfc0ba2d2015-01-01 16:18:15 -0700182 "Use x86 memory type range registers (32-bit only)",
183 "[list] - list current registers\n"
184 "set <reg> <type> <start> <size> - set a register\n"
185 "\t<type> is Uncacheable, Combine, Through, Protect, Back\n"
186 "disable <reg> - disable a register\n"
Simon Glasse643edd2020-07-17 08:48:29 -0600187 "enable <reg> - enable a register\n"
188 "\n"
189 "Precede command with '-c <n>|all' to access a particular hex CPU, e.g.\n"
190 " mtrr -c all list; mtrr -c 2e list"
Simon Glassfc0ba2d2015-01-01 16:18:15 -0700191);