blob: f357f587670b67f0d81cd3d7fed7135f8ad095a8 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glassfc0ba2d2015-01-01 16:18:15 -07002/*
3 * (C) Copyright 2014 Google, Inc
Simon Glassfc0ba2d2015-01-01 16:18:15 -07004 */
5
6#include <common.h>
Simon Glassed38aef2020-05-10 11:40:03 -06007#include <command.h>
Simon Glass7403c262020-07-17 08:48:22 -06008#include <log.h>
Simon Glassfc0ba2d2015-01-01 16:18:15 -07009#include <asm/msr.h>
Simon Glass7403c262020-07-17 08:48:22 -060010#include <asm/mp.h>
Simon Glassfc0ba2d2015-01-01 16:18:15 -070011#include <asm/mtrr.h>
12
13static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
14 "Uncacheable",
15 "Combine",
16 "2",
17 "3",
18 "Through",
19 "Protect",
20 "Back",
21};
22
Simon Glass7403c262020-07-17 08:48:22 -060023static void read_mtrrs(void *arg)
Simon Glassfc0ba2d2015-01-01 16:18:15 -070024{
Simon Glass7403c262020-07-17 08:48:22 -060025 struct mtrr_info *info = arg;
26
27 mtrr_read_all(info);
28}
29
30static int do_mtrr_list(int cpu_select)
31{
32 struct mtrr_info info;
33 int ret;
Simon Glassfc0ba2d2015-01-01 16:18:15 -070034 int i;
35
36 printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||",
37 "Mask ||", "Size ||");
Simon Glass7403c262020-07-17 08:48:22 -060038 memset(&info, '\0', sizeof(info));
39 ret = mp_run_on_cpus(cpu_select, read_mtrrs, &info);
40 if (ret)
41 return log_msg_ret("run", ret);
Simon Glassfc0ba2d2015-01-01 16:18:15 -070042 for (i = 0; i < MTRR_COUNT; i++) {
43 const char *type = "Invalid";
44 uint64_t base, mask, size;
45 bool valid;
46
Simon Glass7403c262020-07-17 08:48:22 -060047 base = info.mtrr[i].base;
48 mask = info.mtrr[i].mask;
Simon Glassfc0ba2d2015-01-01 16:18:15 -070049 size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1);
50 size |= (1 << 12) - 1;
51 size += 1;
52 valid = mask & MTRR_PHYS_MASK_VALID;
53 type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK];
54 printf("%d %-5s %-12s %016llx %016llx %016llx\n", i,
Bin Meng933a29b2015-07-06 16:31:32 +080055 valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK,
56 mask & ~MTRR_PHYS_MASK_VALID, size);
Simon Glassfc0ba2d2015-01-01 16:18:15 -070057 }
58
59 return 0;
60}
61
Simon Glassed38aef2020-05-10 11:40:03 -060062static int do_mtrr_set(uint reg, int argc, char *const argv[])
Simon Glassfc0ba2d2015-01-01 16:18:15 -070063{
64 const char *typename = argv[0];
65 struct mtrr_state state;
66 uint32_t start, size;
67 uint64_t base, mask;
68 int i, type = -1;
69 bool valid;
70
71 if (argc < 3)
72 return CMD_RET_USAGE;
73 for (i = 0; i < MTRR_TYPE_COUNT; i++) {
74 if (*typename == *mtrr_type_name[i])
75 type = i;
76 }
77 if (type == -1) {
78 printf("Invalid type name %s\n", typename);
79 return CMD_RET_USAGE;
80 }
81 start = simple_strtoul(argv[1], NULL, 16);
82 size = simple_strtoul(argv[2], NULL, 16);
83
84 base = start | type;
85 valid = native_read_msr(MTRR_PHYS_MASK_MSR(reg)) & MTRR_PHYS_MASK_VALID;
86 mask = ~((uint64_t)size - 1);
87 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
88 if (valid)
89 mask |= MTRR_PHYS_MASK_VALID;
90
Simon Glass8fafd012018-10-01 12:22:37 -060091 mtrr_open(&state, true);
Simon Glassfc0ba2d2015-01-01 16:18:15 -070092 wrmsrl(MTRR_PHYS_BASE_MSR(reg), base);
93 wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask);
Simon Glass8fafd012018-10-01 12:22:37 -060094 mtrr_close(&state, true);
Simon Glassfc0ba2d2015-01-01 16:18:15 -070095
96 return 0;
97}
98
99static int mtrr_set_valid(int reg, bool valid)
100{
101 struct mtrr_state state;
102 uint64_t mask;
103
Simon Glass8fafd012018-10-01 12:22:37 -0600104 mtrr_open(&state, true);
Simon Glassfc0ba2d2015-01-01 16:18:15 -0700105 mask = native_read_msr(MTRR_PHYS_MASK_MSR(reg));
106 if (valid)
107 mask |= MTRR_PHYS_MASK_VALID;
108 else
109 mask &= ~MTRR_PHYS_MASK_VALID;
110 wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask);
Simon Glass8fafd012018-10-01 12:22:37 -0600111 mtrr_close(&state, true);
Simon Glassfc0ba2d2015-01-01 16:18:15 -0700112
113 return 0;
114}
115
Simon Glassed38aef2020-05-10 11:40:03 -0600116static int do_mtrr(struct cmd_tbl *cmdtp, int flag, int argc,
117 char *const argv[])
Simon Glassfc0ba2d2015-01-01 16:18:15 -0700118{
119 const char *cmd;
Simon Glass7403c262020-07-17 08:48:22 -0600120 int cpu_select;
Simon Glassfc0ba2d2015-01-01 16:18:15 -0700121 uint reg;
122
Simon Glass7403c262020-07-17 08:48:22 -0600123 cpu_select = MP_SELECT_BSP;
Simon Glassfc0ba2d2015-01-01 16:18:15 -0700124 cmd = argv[1];
125 if (argc < 2 || *cmd == 'l')
Simon Glass7403c262020-07-17 08:48:22 -0600126 return do_mtrr_list(cpu_select);
Simon Glassfc0ba2d2015-01-01 16:18:15 -0700127 argc -= 2;
128 argv += 2;
129 if (argc <= 0)
130 return CMD_RET_USAGE;
131 reg = simple_strtoul(argv[0], NULL, 16);
132 if (reg >= MTRR_COUNT) {
133 printf("Invalid register number\n");
134 return CMD_RET_USAGE;
135 }
136 if (*cmd == 'e')
137 return mtrr_set_valid(reg, true);
138 else if (*cmd == 'd')
139 return mtrr_set_valid(reg, false);
140 else if (*cmd == 's')
141 return do_mtrr_set(reg, argc - 1, argv + 1);
142 else
143 return CMD_RET_USAGE;
144
145 return 0;
146}
147
148U_BOOT_CMD(
149 mtrr, 6, 1, do_mtrr,
150 "Use x86 memory type range registers (32-bit only)",
151 "[list] - list current registers\n"
152 "set <reg> <type> <start> <size> - set a register\n"
153 "\t<type> is Uncacheable, Combine, Through, Protect, Back\n"
154 "disable <reg> - disable a register\n"
Simon Glassc947a622020-07-17 08:48:12 -0600155 "enable <reg> - enable a register"
Simon Glassfc0ba2d2015-01-01 16:18:15 -0700156);