Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Przemyslaw Marczak | d5175dc | 2015-05-13 13:38:32 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015 Samsung Electronics |
| 4 | * Przemyslaw Marczak <p.marczak@samsung.com> |
Przemyslaw Marczak | d5175dc | 2015-05-13 13:38:32 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _SANDBOX_PMIC_H_ |
| 8 | #define _SANDBOX_PMIC_H_ |
| 9 | |
| 10 | #define SANDBOX_LDO_DRIVER "sandbox_ldo" |
| 11 | #define SANDBOX_OF_LDO_PREFIX "ldo" |
| 12 | #define SANDBOX_BUCK_DRIVER "sandbox_buck" |
| 13 | #define SANDBOX_OF_BUCK_PREFIX "buck" |
| 14 | |
Felix Brack | e23c388 | 2017-11-27 09:14:16 +0100 | [diff] [blame] | 15 | #define SANDBOX_BUCK_COUNT 3 |
Przemyslaw Marczak | d5175dc | 2015-05-13 13:38:32 +0200 | [diff] [blame] | 16 | #define SANDBOX_LDO_COUNT 2 |
| 17 | /* |
| 18 | * Sandbox PMIC registers: |
| 19 | * We have only 12 significant registers, but we alloc 16 for padding. |
| 20 | */ |
| 21 | enum { |
| 22 | SANDBOX_PMIC_REG_BUCK1_UV = 0, |
| 23 | SANDBOX_PMIC_REG_BUCK1_UA, |
| 24 | SANDBOX_PMIC_REG_BUCK1_OM, |
| 25 | |
| 26 | SANDBOX_PMIC_REG_BUCK2_UV, |
| 27 | SANDBOX_PMIC_REG_BUCK2_UA, |
| 28 | SANDBOX_PMIC_REG_BUCK2_OM, |
| 29 | |
| 30 | SANDBOX_PMIC_REG_LDO_OFFSET, |
| 31 | SANDBOX_PMIC_REG_LDO1_UV = SANDBOX_PMIC_REG_LDO_OFFSET, |
| 32 | SANDBOX_PMIC_REG_LDO1_UA, |
| 33 | SANDBOX_PMIC_REG_LDO1_OM, |
| 34 | |
| 35 | SANDBOX_PMIC_REG_LDO2_UV, |
| 36 | SANDBOX_PMIC_REG_LDO2_UA, |
| 37 | SANDBOX_PMIC_REG_LDO2_OM, |
| 38 | |
| 39 | SANDBOX_PMIC_REG_COUNT = 16, |
| 40 | }; |
| 41 | |
| 42 | /* Register offset for output: micro Volts, micro Amps, Operation Mode */ |
| 43 | enum { |
| 44 | OUT_REG_UV = 0, |
| 45 | OUT_REG_UA, |
| 46 | OUT_REG_OM, |
| 47 | OUT_REG_COUNT, |
| 48 | }; |
| 49 | |
| 50 | /* Buck operation modes */ |
| 51 | enum { |
| 52 | BUCK_OM_OFF = 0, |
| 53 | BUCK_OM_ON, |
| 54 | BUCK_OM_PWM, |
| 55 | BUCK_OM_COUNT, |
| 56 | }; |
| 57 | |
| 58 | /* Ldo operation modes */ |
| 59 | enum { |
| 60 | LDO_OM_OFF = 0, |
| 61 | LDO_OM_ON, |
| 62 | LDO_OM_SLEEP, |
| 63 | LDO_OM_STANDBY, |
| 64 | LDO_OM_COUNT, |
| 65 | }; |
| 66 | |
| 67 | /* BUCK1 Voltage: min: 0.8V, step: 25mV, max 2.4V */ |
| 68 | #define OUT_BUCK1_UV_MIN 800000 |
| 69 | #define OUT_BUCK1_UV_MAX 2400000 |
| 70 | #define OUT_BUCK1_UV_STEP 25000 |
| 71 | |
| 72 | /* BUCK1 Amperage: min: 150mA, step: 25mA, max: 250mA */ |
| 73 | #define OUT_BUCK1_UA_MIN 150000 |
| 74 | #define OUT_BUCK1_UA_MAX 250000 |
| 75 | #define OUT_BUCK1_UA_STEP 25000 |
| 76 | |
| 77 | /* BUCK2 Voltage: min: 0.75V, step: 50mV, max 3.95V */ |
| 78 | #define OUT_BUCK2_UV_MIN 750000 |
| 79 | #define OUT_BUCK2_UV_MAX 3950000 |
| 80 | #define OUT_BUCK2_UV_STEP 50000 |
| 81 | |
| 82 | /* LDO1 Voltage: min: 0.8V, step: 25mV, max 2.4V */ |
| 83 | #define OUT_LDO1_UV_MIN 800000 |
| 84 | #define OUT_LDO1_UV_MAX 2400000 |
| 85 | #define OUT_LDO1_UV_STEP 25000 |
| 86 | |
| 87 | /* LDO1 Amperage: min: 100mA, step: 50mA, max: 200mA */ |
| 88 | #define OUT_LDO1_UA_MIN 100000 |
| 89 | #define OUT_LDO1_UA_MAX 200000 |
| 90 | #define OUT_LDO1_UA_STEP 50000 |
| 91 | |
| 92 | /* LDO2 Voltage: min: 0.75V, step: 50mV, max 3.95V */ |
| 93 | #define OUT_LDO2_UV_MIN 750000 |
| 94 | #define OUT_LDO2_UV_MAX 3950000 |
| 95 | #define OUT_LDO2_UV_STEP 50000 |
| 96 | |
| 97 | /* register <-> value conversion */ |
| 98 | #define REG2VAL(min, step, reg) ((min) + ((step) * (reg))) |
| 99 | #define VAL2REG(min, step, val) (((val) - (min)) / (step)) |
| 100 | |
| 101 | /* Operation mode id -> register value conversion */ |
| 102 | #define OM2REG(x) (x) |
| 103 | |
Przemyslaw Marczak | dca9450 | 2015-05-13 13:38:33 +0200 | [diff] [blame] | 104 | /* Test data for: test/dm/power.c */ |
| 105 | |
| 106 | /* BUCK names */ |
| 107 | #define SANDBOX_BUCK1_DEVNAME "buck1" |
| 108 | #define SANDBOX_BUCK1_PLATNAME "SUPPLY_1.2V" |
| 109 | #define SANDBOX_BUCK2_DEVNAME "buck2" |
| 110 | #define SANDBOX_BUCK2_PLATNAME "SUPPLY_3.3V" |
Felix Brack | e23c388 | 2017-11-27 09:14:16 +0100 | [diff] [blame] | 111 | /* BUCK3: for testing fallback regulator prefix matching during bind */ |
| 112 | #define SANDBOX_BUCK3_DEVNAME "no_match_by_nodename" |
| 113 | #define SANDBOX_BUCK3_PLATNAME "buck_SUPPLY_1.5V" |
Przemyslaw Marczak | dca9450 | 2015-05-13 13:38:33 +0200 | [diff] [blame] | 114 | /* LDO names */ |
| 115 | #define SANDBOX_LDO1_DEVNAME "ldo1" |
| 116 | #define SANDBOX_LDO1_PLATNAME "VDD_EMMC_1.8V" |
| 117 | #define SANDBOX_LDO2_DEVNAME "ldo2" |
| 118 | #define SANDBOX_LDO2_PLATNAME "VDD_LCD_3.3V" |
| 119 | |
| 120 | /* |
| 121 | * Expected regulators setup after call of: |
Simon Glass | 46cb824 | 2015-06-23 15:38:58 -0600 | [diff] [blame] | 122 | * - regulator_autoset_by_name() |
Przemyslaw Marczak | dca9450 | 2015-05-13 13:38:33 +0200 | [diff] [blame] | 123 | * - regulator_list_autoset() |
| 124 | */ |
| 125 | |
Simon Glass | 46cb824 | 2015-06-23 15:38:58 -0600 | [diff] [blame] | 126 | /* BUCK1: for testing regulator_autoset_by_name() */ |
Przemyslaw Marczak | dca9450 | 2015-05-13 13:38:33 +0200 | [diff] [blame] | 127 | #define SANDBOX_BUCK1_AUTOSET_EXPECTED_UV 1200000 |
| 128 | #define SANDBOX_BUCK1_AUTOSET_EXPECTED_UA 200000 |
| 129 | #define SANDBOX_BUCK1_AUTOSET_EXPECTED_ENABLE true |
| 130 | |
Przemyslaw Marczak | 23bc2a7 | 2015-10-27 13:08:07 +0100 | [diff] [blame] | 131 | /* BUCK2: for testing sandbox ADC's supply */ |
| 132 | #define SANDBOX_BUCK2_INITIAL_EXPECTED_UV 3000000 |
| 133 | #define SANDBOX_BUCK2_SET_UV 3300000 |
| 134 | |
Przemyslaw Marczak | dca9450 | 2015-05-13 13:38:33 +0200 | [diff] [blame] | 135 | /* LDO1/2 for testing regulator_list_autoset() */ |
| 136 | #define SANDBOX_LDO1_AUTOSET_EXPECTED_UV 1800000 |
| 137 | #define SANDBOX_LDO1_AUTOSET_EXPECTED_UA 100000 |
| 138 | #define SANDBOX_LDO1_AUTOSET_EXPECTED_ENABLE true |
| 139 | |
| 140 | #define SANDBOX_LDO2_AUTOSET_EXPECTED_UV 3000000 |
| 141 | #define SANDBOX_LDO2_AUTOSET_EXPECTED_UA -ENOSYS |
| 142 | #define SANDBOX_LDO2_AUTOSET_EXPECTED_ENABLE false |
| 143 | |
Przemyslaw Marczak | d5175dc | 2015-05-13 13:38:32 +0200 | [diff] [blame] | 144 | #endif |