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Siew Chin Lim954d5992021-03-24 13:11:34 +08001/* SPDX-License-Identifier: GPL-2.0
2 *
Siew Chin Lim02d25002021-03-24 13:11:37 +08003 * Copyright (C) 2016-2020 Intel Corporation <www.intel.com>
Siew Chin Lim954d5992021-03-24 13:11:34 +08004 *
5 */
6
7#ifndef _HANDOFF_SOC64_H_
8#define _HANDOFF_SOC64_H_
9
10/*
11 * Offset for HW handoff from Quartus tools
12 */
Siew Chin Lim02d25002021-03-24 13:11:37 +080013/* HPS handoff */
Siew Chin Lim954d5992021-03-24 13:11:34 +080014#define SOC64_HANDOFF_MAGIC_MUX 0x504D5558
15#define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354
16#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741
17#define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159
18#define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53
19#define SOC64_HANDOFF_MAGIC_MISC 0x4D495343
Siew Chin Lim02d25002021-03-24 13:11:37 +080020
Siew Chin Lim954d5992021-03-24 13:11:34 +080021#define SOC64_HANDOFF_OFFSET_LENGTH 0x4
22#define SOC64_HANDOFF_OFFSET_DATA 0x10
Siew Chin Lim02d25002021-03-24 13:11:37 +080023#define SOC64_HANDOFF_SIZE 4096
24
25#define SOC64_HANDOFF_BASE 0xFFE3F000
26#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
27#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10)
28#define SOC64_HANDOFF_IOCTL (SOC64_HANDOFF_BASE + 0x1A0)
29#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
30#define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0)
31#define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580)
Siew Chin Lim954d5992021-03-24 13:11:34 +080032
33#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
34#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608)
35#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C)
36#else
37#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x5fc)
38#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600)
39#endif
40
Siew Chin Lim954d5992021-03-24 13:11:34 +080041#endif /* _HANDOFF_SOC64_H_ */