Park, Aiden | 6e3cc36 | 2019-08-03 08:30:12 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2019 Intel Corporation <www.intel.com> |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | 1fa70f8 | 2019-11-14 12:57:34 -0700 | [diff] [blame] | 7 | #include <cpu_func.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 8 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 9 | #include <log.h> |
Park, Aiden | 347f1b4 | 2019-08-03 08:30:52 +0000 | [diff] [blame] | 10 | #include <asm/arch/slimbootloader.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 11 | #include <asm/global_data.h> |
Park, Aiden | 347f1b4 | 2019-08-03 08:30:52 +0000 | [diff] [blame] | 12 | |
| 13 | DECLARE_GLOBAL_DATA_PTR; |
| 14 | |
| 15 | /** |
| 16 | * This sets tsc_base and clock_rate for early_timer and tsc_timer. |
| 17 | * The performance info guid hob has all performance timestamp data, but |
| 18 | * the only tsc frequency info is used for the timer driver for now. |
| 19 | * |
| 20 | * Slim Bootloader already calibrated TSC and provides it to U-Boot. |
| 21 | * Therefore, U-Boot does not have to re-calibrate TSC. |
| 22 | * Configuring tsc_base and clock_rate here makes x86 tsc_timer driver |
| 23 | * bypass TSC calibration and use the provided TSC frequency. |
| 24 | */ |
| 25 | static void tsc_init(void) |
| 26 | { |
| 27 | struct sbl_performance_info *data; |
| 28 | const efi_guid_t guid = SBL_PERFORMANCE_INFO_GUID; |
| 29 | |
| 30 | if (!gd->arch.hob_list) |
| 31 | panic("hob list not found!"); |
| 32 | |
| 33 | gd->arch.tsc_base = rdtsc(); |
| 34 | debug("tsc_base=0x%llx\n", gd->arch.tsc_base); |
| 35 | |
| 36 | data = hob_get_guid_hob_data(gd->arch.hob_list, NULL, &guid); |
| 37 | if (!data) { |
| 38 | debug("performance info hob not found\n"); |
| 39 | return; |
| 40 | } |
| 41 | |
| 42 | /* frequency is in KHz, so to Hz */ |
| 43 | gd->arch.clock_rate = data->frequency * 1000; |
| 44 | debug("freq=0x%lx\n", gd->arch.clock_rate); |
| 45 | } |
Park, Aiden | 6e3cc36 | 2019-08-03 08:30:12 +0000 | [diff] [blame] | 46 | |
| 47 | int arch_cpu_init(void) |
| 48 | { |
Park, Aiden | 347f1b4 | 2019-08-03 08:30:52 +0000 | [diff] [blame] | 49 | tsc_init(); |
| 50 | |
Park, Aiden | 6e3cc36 | 2019-08-03 08:30:12 +0000 | [diff] [blame] | 51 | return x86_cpu_init_f(); |
| 52 | } |
| 53 | |
| 54 | int checkcpu(void) |
| 55 | { |
| 56 | return 0; |
| 57 | } |
| 58 | |
| 59 | int print_cpuinfo(void) |
| 60 | { |
| 61 | return default_print_cpuinfo(); |
| 62 | } |