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git01.mediatek.com / filogic / uboot / 0275862f7bc6f5e894bc3ca02557963b7d25c8cb / . / drivers / block / sata_sil.h
blob: 2dfd4a5e549aedccbdb328fbeb5c07c9732ffe5b [file] [log] [blame]
Tang Yuantian4511ccc2011-10-07 19:26:58 +0000[diff] [blame]1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Author: Tang Yuantian <b29983@freescale.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#ifndef SATA_SIL3132_H
22#define SATA_SIL3132_H
23
24#define READ_CMD 0
25#define WRITE_CMD 1
26
27extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
28
29/*
30 * SATA device driver struct for each dev
31 */
32struct sil_sata {
33 char name[12];
34 void *port; /* the port base address */
35 int lba48;
36 u16 pio;
37 u16 mwdma;
38 u16 udma;
39 pci_dev_t devno;
40 int wcache;
41 int flush;
42 int flush_ext;
43};
44
45/* sata info for each controller */
46struct sata_info {
47 ulong iobase[3];
48 pci_dev_t devno;
49 int portbase;
50 int maxport;
51};
52
53/*
54 * Scatter gather entry (SGE),MUST 8 bytes aligned
55 */
56struct sil_sge {
57 __le64 addr;
58 __le32 cnt;
59 __le32 flags;
60} __attribute__ ((aligned(8), packed));
61
62/*
63 * Port request block, MUST 8 bytes aligned
64 */
65struct sil_prb {
66 __le16 ctrl;
67 __le16 prot;
68 __le32 rx_cnt;
69 struct sata_fis_h2d fis;
70} __attribute__ ((aligned(8), packed));
71
72struct sil_cmd_block {
73 struct sil_prb prb;
74 struct sil_sge sge;
75};
76
77enum {
78 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
79 HOST_CTRL = 0x40,
80 HOST_IRQ_STAT = 0x44,
81 HOST_PHY_CFG = 0x48,
82 HOST_BIST_CTRL = 0x50,
83 HOST_BIST_PTRN = 0x54,
84 HOST_BIST_STAT = 0x58,
85 HOST_MEM_BIST_STAT = 0x5c,
86 HOST_FLASH_CMD = 0x70,
87 /* 8 bit regs */
88 HOST_FLASH_DATA = 0x74,
89 HOST_TRANSITION_DETECT = 0x75,
90 HOST_GPIO_CTRL = 0x76,
91 HOST_I2C_ADDR = 0x78, /* 32 bit */
92 HOST_I2C_DATA = 0x7c,
93 HOST_I2C_XFER_CNT = 0x7e,
94 HOST_I2C_CTRL = 0x7f,
95
96 /* HOST_SLOT_STAT bits */
97 HOST_SSTAT_ATTN = (1 << 31),
98
99 /* HOST_CTRL bits */
100 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
101 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
102 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
103 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
104 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
105 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
106
107 /*
108 * Port registers
109 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
110 */
111 PORT_REGS_SIZE = 0x2000,
112
113 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
114 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
115
116 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
117 PORT_PMP_STATUS = 0x0000, /* port device status offset */
118 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
119 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
120
121 /* 32 bit regs */
122 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
123 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
124 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
125 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
126 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
127 PORT_ACTIVATE_UPPER_ADDR = 0x101c,
128 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
129 PORT_CMD_ERR = 0x1024, /* command error number */
130 PORT_FIS_CFG = 0x1028,
131 PORT_FIFO_THRES = 0x102c,
132
133 /* 16 bit regs */
134 PORT_DECODE_ERR_CNT = 0x1040,
135 PORT_DECODE_ERR_THRESH = 0x1042,
136 PORT_CRC_ERR_CNT = 0x1044,
137 PORT_CRC_ERR_THRESH = 0x1046,
138 PORT_HSHK_ERR_CNT = 0x1048,
139 PORT_HSHK_ERR_THRESH = 0x104a,
140
141 /* 32 bit regs */
142 PORT_PHY_CFG = 0x1050,
143 PORT_SLOT_STAT = 0x1800,
144 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 */
145 PORT_CONTEXT = 0x1e04,
146 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 */
147 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 */
148 PORT_SCONTROL = 0x1f00,
149 PORT_SSTATUS = 0x1f04,
150 PORT_SERROR = 0x1f08,
151 PORT_SACTIVE = 0x1f0c,
152
153 /* PORT_CTRL_STAT bits */
154 PORT_CS_PORT_RST = (1 << 0), /* port reset */
155 PORT_CS_DEV_RST = (1 << 1), /* device reset */
156 PORT_CS_INIT = (1 << 2), /* port initialize */
157 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
158 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
159 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
160 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
161 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
162 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
163
164 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
165 /* bits[11:0] are masked */
166 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
167 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
168 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
169 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
170 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
171 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
172 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
173 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
174 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
175 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
176 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
177 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
178
179 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
180 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
181 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
182
183 /* bits[27:16] are unmasked (raw) */
184 PORT_IRQ_RAW_SHIFT = 16,
185 PORT_IRQ_MASKED_MASK = 0x7ff,
186 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
187
188 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
189 PORT_IRQ_STEER_SHIFT = 30,
190 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
191
192 /* PORT_CMD_ERR constants */
193 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
194 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
195 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
196 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
197 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
198 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
199 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
200 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
201
202 /* bits of PRB control field */
203 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
204 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
205 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
206 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
207 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
208
209 /* PRB protocol field */
210 PRB_PROT_PACKET = (1 << 0),
211 PRB_PROT_TCQ = (1 << 1),
212 PRB_PROT_NCQ = (1 << 2),
213 PRB_PROT_READ = (1 << 3),
214 PRB_PROT_WRITE = (1 << 4),
215 PRB_PROT_TRANSPARENT = (1 << 5),
216
217 /*
218 * Other constants
219 */
220 SGE_TRM = (1 << 31), /* Last SGE in chain */
221 SGE_LNK = (1 << 30), /* linked list
222 Points to SGT, not SGE */
223 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
224 data address ignored */
225
226 CMD_ERR = 0x21,
227};
228
229#endif