Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Stelian Pop | d1aea1c | 2008-01-30 21:15:54 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2007-2008 |
Stelian Pop | 5ee0c7f | 2011-11-01 00:00:39 +0100 | [diff] [blame] | 4 | * Stelian Pop <stelian@popies.net> |
Stelian Pop | d1aea1c | 2008-01-30 21:15:54 +0000 | [diff] [blame] | 5 | * Lead Tech Design <www.leadtechdesign.com> |
Stelian Pop | d1aea1c | 2008-01-30 21:15:54 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
Reinhard Meyer | b06208c | 2010-11-07 13:26:14 +0100 | [diff] [blame] | 9 | #include <asm/io.h> |
Stelian Pop | d1aea1c | 2008-01-30 21:15:54 +0000 | [diff] [blame] | 10 | #include <asm/arch/hardware.h> |
Stelian Pop | d4bfbc5 | 2008-03-26 20:52:32 +0100 | [diff] [blame] | 11 | #include <asm/arch/at91_pit.h> |
Jean-Christophe PLAGNIOL-VILLARD | 1d4a379 | 2009-04-16 21:30:48 +0200 | [diff] [blame] | 12 | #include <asm/arch/clk.h> |
Jean-Christophe PLAGNIOL-VILLARD | 1d4a379 | 2009-04-16 21:30:48 +0200 | [diff] [blame] | 13 | #include <div64.h> |
Stelian Pop | d1aea1c | 2008-01-30 21:15:54 +0000 | [diff] [blame] | 14 | |
Reinhard Meyer | 0a1790a | 2010-10-05 16:54:35 +0200 | [diff] [blame] | 15 | #if !defined(CONFIG_AT91FAMILY) |
| 16 | # error You need to define CONFIG_AT91FAMILY in your board config! |
| 17 | #endif |
| 18 | |
| 19 | DECLARE_GLOBAL_DATA_PTR; |
| 20 | |
Stelian Pop | d1aea1c | 2008-01-30 21:15:54 +0000 | [diff] [blame] | 21 | /* |
Stelian Pop | eea44aa | 2008-03-26 20:52:28 +0100 | [diff] [blame] | 22 | * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by |
Stelian Pop | d1aea1c | 2008-01-30 21:15:54 +0000 | [diff] [blame] | 23 | * setting the 20 bit counter period to its maximum (0xfffff). |
Reinhard Meyer | 0a1790a | 2010-10-05 16:54:35 +0200 | [diff] [blame] | 24 | * (See the relevant data sheets to understand that this really works) |
| 25 | * |
| 26 | * We do also mimic the typical powerpc way of incrementing |
| 27 | * two 32 bit registers called tbl and tbu. |
| 28 | * |
| 29 | * Those registers increment at 1/16 the main clock rate. |
Stelian Pop | d1aea1c | 2008-01-30 21:15:54 +0000 | [diff] [blame] | 30 | */ |
Stelian Pop | d1aea1c | 2008-01-30 21:15:54 +0000 | [diff] [blame] | 31 | |
Reinhard Meyer | 0a1790a | 2010-10-05 16:54:35 +0200 | [diff] [blame] | 32 | #define TIMER_LOAD_VAL 0xfffff |
Jean-Christophe PLAGNIOL-VILLARD | 1d4a379 | 2009-04-16 21:30:48 +0200 | [diff] [blame] | 33 | |
Reinhard Meyer | 0a1790a | 2010-10-05 16:54:35 +0200 | [diff] [blame] | 34 | /* |
| 35 | * Use the PITC in full 32 bit incrementing mode |
| 36 | */ |
Stelian Pop | 6bf2de2 | 2008-03-26 21:52:27 +0100 | [diff] [blame] | 37 | int timer_init(void) |
Stelian Pop | d1aea1c | 2008-01-30 21:15:54 +0000 | [diff] [blame] | 38 | { |
Reinhard Meyer | e260d0b | 2010-11-03 15:39:55 +0100 | [diff] [blame] | 39 | at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; |
Reinhard Meyer | 0a1790a | 2010-10-05 16:54:35 +0200 | [diff] [blame] | 40 | |
Wenyou Yang | 57b7f29 | 2016-02-03 10:16:49 +0800 | [diff] [blame] | 41 | at91_periph_clk_enable(ATMEL_ID_SYS); |
Stelian Pop | d1aea1c | 2008-01-30 21:15:54 +0000 | [diff] [blame] | 42 | |
| 43 | /* Enable PITC */ |
Jens Scharsig | a4db1ca | 2010-02-03 22:46:58 +0100 | [diff] [blame] | 44 | writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); |
Stelian Pop | d1aea1c | 2008-01-30 21:15:54 +0000 | [diff] [blame] | 45 | |
Simon Glass | 6ed6e03 | 2012-12-13 20:48:32 +0000 | [diff] [blame] | 46 | gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16; |
Jean-Christophe PLAGNIOL-VILLARD | 1d4a379 | 2009-04-16 21:30:48 +0200 | [diff] [blame] | 47 | |
Stelian Pop | d1aea1c | 2008-01-30 21:15:54 +0000 | [diff] [blame] | 48 | return 0; |
| 49 | } |
| 50 | |
| 51 | /* |
Reinhard Meyer | 0a1790a | 2010-10-05 16:54:35 +0200 | [diff] [blame] | 52 | * Return the number of timer ticks per second. |
Stelian Pop | d1aea1c | 2008-01-30 21:15:54 +0000 | [diff] [blame] | 53 | */ |
| 54 | ulong get_tbclk(void) |
| 55 | { |
Simon Glass | 6ed6e03 | 2012-12-13 20:48:32 +0000 | [diff] [blame] | 56 | return gd->arch.timer_rate_hz; |
Stelian Pop | d1aea1c | 2008-01-30 21:15:54 +0000 | [diff] [blame] | 57 | } |