blob: cab402a484caf505adaa8775aa6bda9e2e3ecd35 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Peter Howard9ed4f702015-03-23 09:19:56 +11002/*
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on davinci_dvevm.h. Original Copyrights follow:
6 *
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
Peter Howard9ed4f702015-03-23 09:19:56 +11008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/*
14 * Board
15 */
Peter Howard9ed4f702015-03-23 09:19:56 +110016#undef CONFIG_USE_SPIFLASH
17#undef CONFIG_SYS_USE_NOR
Peter Howard9ed4f702015-03-23 09:19:56 +110018
19/*
20 * SoC Configuration
21 */
22#define CONFIG_MACH_OMAPL138_LCDK
Peter Howard9ed4f702015-03-23 09:19:56 +110023#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
24#define CONFIG_SYS_OSCIN_FREQ 24000000
25#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
26#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
27#define CONFIG_SYS_HZ 1000
28#define CONFIG_SKIP_LOWLEVEL_INIT
Peter Howard9ed4f702015-03-23 09:19:56 +110029
30/*
31 * Memory Info
32 */
33#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
34#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
35#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
36#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
37
Adam Ford1264bdf2019-02-25 21:53:46 -060038#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
39#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
40
Peter Howard9ed4f702015-03-23 09:19:56 +110041/* memtest start addr */
42#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
43
44/* memtest will be run on 16MB */
45#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
46
Peter Howard9ed4f702015-03-23 09:19:56 +110047#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
48 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
49 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
50 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
51 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
52 DAVINCI_SYSCFG_SUSPSRC_I2C)
53
54/*
55 * PLL configuration
56 */
Peter Howard9ed4f702015-03-23 09:19:56 +110057
David Lechner5425f2d2018-03-14 20:36:30 -050058/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
59#define CONFIG_SYS_DA850_PLL0_PLLM 18
Peter Howard9ed4f702015-03-23 09:19:56 +110060#define CONFIG_SYS_DA850_PLL1_PLLM 21
61
62/*
Fabien Parent7b3cece2016-11-29 14:23:39 +010063 * DDR2 memory configuration
64 */
65#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
66 DV_DDR_PHY_EXT_STRBEN | \
67 (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
68
69#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
70 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
71 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
72 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
73 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
74 (4 << DV_DDR_SDCR_CL_SHIFT) | \
75 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
76 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
77
78/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
79#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
80
81#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
82 (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
83 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
84 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
85 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
86 (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
87 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
88 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
89 (1 << DV_DDR_SDTMR1_WTR_SHIFT))
90
91#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
92 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
93 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
94 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
Sekhar Norid53dbf32017-06-02 18:07:12 +053095 (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
Fabien Parent7b3cece2016-11-29 14:23:39 +010096 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
97 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
98 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
99
100#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
101#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
102
103/*
Peter Howard9ed4f702015-03-23 09:19:56 +1100104 * Serial Driver info
105 */
Lokesh Vutlad601a6e2018-03-16 18:52:21 +0530106#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
107#if !defined(CONFIG_DM_SERIAL)
Peter Howard9ed4f702015-03-23 09:19:56 +1100108#define CONFIG_SYS_NS16550_SERIAL
109#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
110#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
111#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
Peter Howard9ed4f702015-03-23 09:19:56 +1100112#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Lokesh Vutlad601a6e2018-03-16 18:52:21 +0530113#endif
Peter Howard9ed4f702015-03-23 09:19:56 +1100114
Peter Howard9ed4f702015-03-23 09:19:56 +1100115#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
116#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
Peter Howard9ed4f702015-03-23 09:19:56 +1100117
118#ifdef CONFIG_USE_SPIFLASH
Peter Howard9ed4f702015-03-23 09:19:56 +1100119#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
120#endif
121
122/*
123 * I2C Configuration
124 */
Peter Howard9ed4f702015-03-23 09:19:56 +1100125#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
126#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
127#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
128
129/*
130 * Flash & Environment
131 */
Adam Fordfc3ad5b2018-07-10 06:47:33 -0500132#ifdef CONFIG_NAND
Peter Howard9ed4f702015-03-23 09:19:56 +1100133#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
134#define CONFIG_ENV_SIZE (128 << 9)
Peter Howard9ed4f702015-03-23 09:19:56 +1100135#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
136#define CONFIG_SYS_NAND_PAGE_2K
Peter Howard9ed4f702015-03-23 09:19:56 +1100137#define CONFIG_SYS_NAND_CS 3
138#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
Fabien Parentfd429162016-11-29 14:31:31 +0100139#define CONFIG_SYS_NAND_MASK_CLE 0x10
Fabien Parent5e0e3ce2016-11-29 14:31:32 +0100140#define CONFIG_SYS_NAND_MASK_ALE 0x8
Peter Howard9ed4f702015-03-23 09:19:56 +1100141#undef CONFIG_SYS_NAND_HW_ECC
142#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Fabien Parenta2e4dac2016-11-29 14:31:34 +0100143#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
Fabien Parent7f040722016-12-05 19:15:21 +0100144#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
Fabien Parenta2e4dac2016-11-29 14:31:34 +0100145#define CONFIG_SYS_NAND_5_ADDR_CYCLE
146#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
147#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
Fabien Parenta1bd5122016-12-05 19:15:20 +0100148#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
Fabien Parenta2e4dac2016-11-29 14:31:34 +0100149#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
150#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
151#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
152 CONFIG_SYS_NAND_U_BOOT_SIZE - \
153 CONFIG_SYS_MALLOC_LEN - \
154 GENERATED_GBL_DATA_SIZE)
155#define CONFIG_SYS_NAND_ECCPOS { \
Fabien Parent7f040722016-12-05 19:15:21 +0100156 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
157 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
158 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
159 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
Fabien Parenta2e4dac2016-11-29 14:31:34 +0100160#define CONFIG_SYS_NAND_PAGE_COUNT 64
161#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
162#define CONFIG_SYS_NAND_ECCSIZE 512
163#define CONFIG_SYS_NAND_ECCBYTES 10
164#define CONFIG_SYS_NAND_OOBSIZE 64
165#define CONFIG_SPL_NAND_BASE
166#define CONFIG_SPL_NAND_DRIVERS
167#define CONFIG_SPL_NAND_ECC
Fabien Parenta2e4dac2016-11-29 14:31:34 +0100168#define CONFIG_SPL_NAND_LOAD
Peter Howard9ed4f702015-03-23 09:19:56 +1100169#endif
170
171#ifdef CONFIG_SYS_USE_NOR
Peter Howard9ed4f702015-03-23 09:19:56 +1100172#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
173#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
174#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
175#define CONFIG_ENV_SIZE (128 << 10)
176#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
177#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
178#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
179 + 3)
180#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
181#endif
182
183#ifdef CONFIG_USE_SPIFLASH
Peter Howard9ed4f702015-03-23 09:19:56 +1100184#define CONFIG_ENV_SIZE (64 << 10)
185#define CONFIG_ENV_OFFSET (256 << 10)
186#define CONFIG_ENV_SECT_SIZE (64 << 10)
Peter Howard9ed4f702015-03-23 09:19:56 +1100187#endif
188
189/*
190 * Network & Ethernet Configuration
191 */
192#ifdef CONFIG_DRIVER_TI_EMAC
Peter Howard9ed4f702015-03-23 09:19:56 +1100193#undef CONFIG_DRIVER_TI_EMAC_USE_RMII
194#define CONFIG_BOOTP_DEFAULT
Peter Howard9ed4f702015-03-23 09:19:56 +1100195#define CONFIG_BOOTP_DNS2
196#define CONFIG_BOOTP_SEND_HOSTNAME
197#define CONFIG_NET_RETRY_COUNT 10
Peter Howard9ed4f702015-03-23 09:19:56 +1100198#endif
199
200/*
201 * U-Boot general configuration
202 */
Fabien Parent93eded52016-12-06 15:45:09 +0100203#define CONFIG_BOOTFILE "zImage" /* Boot file name */
Peter Howard9ed4f702015-03-23 09:19:56 +1100204#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Peter Howard9ed4f702015-03-23 09:19:56 +1100205#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
206#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
Peter Howard9ed4f702015-03-23 09:19:56 +1100207
208/*
Adam Forde95dd042019-08-12 16:45:21 -0500209 * USB Configs
210 */
211#define CONFIG_USB_OHCI_NEW
212#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
213
214/*
Peter Howard9ed4f702015-03-23 09:19:56 +1100215 * Linux Information
216 */
217#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
218#define CONFIG_CMDLINE_TAG
219#define CONFIG_REVISION_TAG
220#define CONFIG_SETUP_MEMORY_TAGS
Fabien Parent79f015a2016-11-29 17:15:02 +0100221#define CONFIG_BOOTCOMMAND \
Sekhar Nori5bf93902017-04-06 14:52:57 +0530222 "run envboot; " \
Sekhar Nori1fc31f72017-04-06 14:52:53 +0530223 "run mmcboot; "
Sekhar Norib261dce2017-04-06 14:52:55 +0530224
225#define DEFAULT_LINUX_BOOT_ENV \
226 "loadaddr=0xc0700000\0" \
Fabien Parent6b70b132016-11-29 17:15:03 +0100227 "fdtaddr=0xc0600000\0" \
Sekhar Norib261dce2017-04-06 14:52:55 +0530228 "scriptaddr=0xc0600000\0"
229
Sekhar Nori5bf93902017-04-06 14:52:57 +0530230#include <environment/ti/mmc.h>
231
Sekhar Norib261dce2017-04-06 14:52:55 +0530232#define CONFIG_EXTRA_ENV_SETTINGS \
233 DEFAULT_LINUX_BOOT_ENV \
Sekhar Nori5bf93902017-04-06 14:52:57 +0530234 DEFAULT_MMC_TI_ARGS \
235 "bootpart=0:2\0" \
236 "bootdir=/boot\0" \
237 "bootfile=zImage\0" \
Fabien Parent6b70b132016-11-29 17:15:03 +0100238 "fdtfile=da850-lcdk.dtb\0" \
Sekhar Nori5bf93902017-04-06 14:52:57 +0530239 "boot_fdt=yes\0" \
240 "boot_fit=0\0" \
241 "console=ttyS2,115200n8\0"
Peter Howard9ed4f702015-03-23 09:19:56 +1100242
Peter Howard9ed4f702015-03-23 09:19:56 +1100243#ifdef CONFIG_CMD_BDI
244#define CONFIG_CLOCKS
245#endif
246
Adam Fordfc3ad5b2018-07-10 06:47:33 -0500247#if !defined(CONFIG_NAND) && \
Peter Howard9ed4f702015-03-23 09:19:56 +1100248 !defined(CONFIG_SYS_USE_NOR) && \
249 !defined(CONFIG_USE_SPIFLASH)
Peter Howard9ed4f702015-03-23 09:19:56 +1100250#define CONFIG_ENV_SIZE (16 << 10)
Peter Howard9ed4f702015-03-23 09:19:56 +1100251#endif
252
253/* SD/MMC */
Peter Howard9ed4f702015-03-23 09:19:56 +1100254
255#ifdef CONFIG_ENV_IS_IN_MMC
256#undef CONFIG_ENV_SIZE
257#undef CONFIG_ENV_OFFSET
258#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
259#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
Peter Howard9ed4f702015-03-23 09:19:56 +1100260#endif
261
262#ifndef CONFIG_DIRECT_NOR_BOOT
263/* defines for SPL */
Peter Howard9ed4f702015-03-23 09:19:56 +1100264#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
265 CONFIG_SYS_MALLOC_LEN)
266#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
Peter Howard9ed4f702015-03-23 09:19:56 +1100267#define CONFIG_SPL_STACK 0x8001ff00
Peter Howard9ed4f702015-03-23 09:19:56 +1100268#define CONFIG_SPL_MAX_FOOTPRINT 32768
269#define CONFIG_SPL_PAD_TO 32768
270#endif
271
272/* additions for new relocation code, must added to all boards */
273#define CONFIG_SYS_SDRAM_BASE 0xc0000000
274#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
275 GENERATED_GBL_DATA_SIZE)
Simon Glassce3574f2017-05-17 08:23:09 -0600276
277#include <asm/arch/hardware.h>
278
Peter Howard9ed4f702015-03-23 09:19:56 +1100279#endif /* __CONFIG_H */