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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mike Rapoport8abe7302010-12-18 17:43:19 -05002/*
Nikita Kiryanov0630b032012-01-02 04:01:30 +00003 * (C) Copyright 2011 CompuLab, Ltd.
Mike Rapoport8abe7302010-12-18 17:43:19 -05004 * Mike Rapoport <mike@compulab.co.il>
Igor Grinbergbebedbf2011-04-18 17:48:31 -04005 * Igor Grinberg <grinberg@compulab.co.il>
Mike Rapoport8abe7302010-12-18 17:43:19 -05006 *
7 * Based on omap3_beagle.h
8 * (C) Copyright 2006-2008
9 * Texas Instruments.
10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Syed Mohammed Khasim <x0khasim@ti.com>
12 *
Igor Grinberg05a96a42011-04-18 17:55:21 -040013 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
Mike Rapoport8abe7302010-12-18 17:43:19 -050014 */
15
16#ifndef __CONFIG_H
17#define __CONFIG_H
18
Albert ARIBAUDbf9032a2016-01-27 08:46:11 +010019#define CONFIG_SYS_CACHELINE_SIZE 64
20
Mike Rapoport8abe7302010-12-18 17:43:19 -050021/*
22 * High Level Configuration Options
23 */
Nikita Kiryanov0630b032012-01-02 04:01:30 +000024#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
Mike Rapoport8abe7302010-12-18 17:43:19 -050025
Mike Rapoport8abe7302010-12-18 17:43:19 -050026#include <asm/arch/cpu.h> /* get chip and board defs */
Nishanth Menonfa96c962015-03-09 17:12:04 -050027#include <asm/arch/omap.h>
Mike Rapoport8abe7302010-12-18 17:43:19 -050028
Mike Rapoport8abe7302010-12-18 17:43:19 -050029/* Clock Defines */
30#define V_OSCK 26000000 /* Clock output from T2 */
31#define V_SCLK (V_OSCK >> 1)
32
Nikita Kiryanov0630b032012-01-02 04:01:30 +000033#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
34#define CONFIG_SETUP_MEMORY_TAGS
35#define CONFIG_INITRD_TAG
36#define CONFIG_REVISION_TAG
Nikita Kiryanovb47cb9d2012-01-12 03:26:30 +000037#define CONFIG_SERIAL_TAG
Mike Rapoport8abe7302010-12-18 17:43:19 -050038
39/*
40 * Size of malloc() pool
41 */
Nikita Kiryanov0630b032012-01-02 04:01:30 +000042 /* Sector */
43#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
Mike Rapoport8abe7302010-12-18 17:43:19 -050044
45/*
46 * Hardware drivers
47 */
48
49/*
50 * NS16550 Configuration
51 */
52#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
53
Mike Rapoport8abe7302010-12-18 17:43:19 -050054#define CONFIG_SYS_NS16550_SERIAL
55#define CONFIG_SYS_NS16550_REG_SIZE (-4)
56#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
57
58/*
59 * select serial console configuration
60 */
Mike Rapoport8abe7302010-12-18 17:43:19 -050061#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
Mike Rapoport8abe7302010-12-18 17:43:19 -050062
63/* allow to overwrite serial and ethaddr */
64#define CONFIG_ENV_OVERWRITE
Mike Rapoport8abe7302010-12-18 17:43:19 -050065#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
66 115200}
Nikita Kiryanov0630b032012-01-02 04:01:30 +000067
Mike Rapoport8abe7302010-12-18 17:43:19 -050068/* USB device configuration */
Nikita Kiryanov0630b032012-01-02 04:01:30 +000069#define CONFIG_USB_DEVICE
70#define CONFIG_USB_TTY
Mike Rapoport8abe7302010-12-18 17:43:19 -050071
72/* commands to include */
Mike Rapoport8abe7302010-12-18 17:43:19 -050073
Heiko Schocherf53f2b82013-10-22 11:03:18 +020074#define CONFIG_SYS_I2C
Nikita Kiryanovb47cb9d2012-01-12 03:26:30 +000075#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
76#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
Nikita Kiryanova8eeecb2014-08-20 15:08:52 +030077#define CONFIG_SYS_I2C_EEPROM_BUS 0
Nikita Kiryanovda4da302012-04-02 02:29:31 +000078#define CONFIG_I2C_MULTI_BUS
Mike Rapoport8abe7302010-12-18 17:43:19 -050079
80/*
81 * TWL4030
82 */
Mike Rapoport8abe7302010-12-18 17:43:19 -050083
84/*
85 * Board NAND Info.
86 */
Mike Rapoport8abe7302010-12-18 17:43:19 -050087#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
88 /* to access nand at */
89 /* CS0 */
Mike Rapoport8abe7302010-12-18 17:43:19 -050090#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
91 /* devices */
Stefan Roese55503c12014-03-11 17:04:45 +010092
Mike Rapoport8abe7302010-12-18 17:43:19 -050093/* Environment information */
Mike Rapoport8abe7302010-12-18 17:43:19 -050094#define CONFIG_EXTRA_ENV_SETTINGS \
95 "loadaddr=0x82000000\0" \
96 "usbtty=cdc_acm\0" \
Nikita Kiryanove4361e92013-12-11 18:04:40 +020097 "console=ttyO2,115200n8\0" \
Mike Rapoport8abe7302010-12-18 17:43:19 -050098 "mpurate=500\0" \
99 "vram=12M\0" \
100 "dvimode=1024x768MR-16@60\0" \
101 "defaultdisplay=dvi\0" \
102 "mmcdev=0\0" \
103 "mmcroot=/dev/mmcblk0p2 rw\0" \
Igor Grinberg23964602013-04-22 01:06:55 +0000104 "mmcrootfstype=ext4 rootwait\0" \
Mike Rapoport8abe7302010-12-18 17:43:19 -0500105 "nandroot=/dev/mtdblock4 rw\0" \
Igor Grinberg23964602013-04-22 01:06:55 +0000106 "nandrootfstype=ubifs\0" \
Mike Rapoport8abe7302010-12-18 17:43:19 -0500107 "mmcargs=setenv bootargs console=${console} " \
108 "mpurate=${mpurate} " \
109 "vram=${vram} " \
110 "omapfb.mode=dvi:${dvimode} " \
Mike Rapoport8abe7302010-12-18 17:43:19 -0500111 "omapdss.def_disp=${defaultdisplay} " \
112 "root=${mmcroot} " \
113 "rootfstype=${mmcrootfstype}\0" \
114 "nandargs=setenv bootargs console=${console} " \
115 "mpurate=${mpurate} " \
116 "vram=${vram} " \
117 "omapfb.mode=dvi:${dvimode} " \
Mike Rapoport8abe7302010-12-18 17:43:19 -0500118 "omapdss.def_disp=${defaultdisplay} " \
119 "root=${nandroot} " \
120 "rootfstype=${nandrootfstype}\0" \
121 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
122 "bootscript=echo Running bootscript from mmc ...; " \
123 "source ${loadaddr}\0" \
124 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
125 "mmcboot=echo Booting from mmc ...; " \
126 "run mmcargs; " \
127 "bootm ${loadaddr}\0" \
128 "nandboot=echo Booting from nand ...; " \
129 "run nandargs; " \
Igor Grinberg23964602013-04-22 01:06:55 +0000130 "nand read ${loadaddr} 2a0000 400000; " \
Mike Rapoport8abe7302010-12-18 17:43:19 -0500131 "bootm ${loadaddr}\0" \
132
133#define CONFIG_BOOTCOMMAND \
Andrew Bradforde1c7c8a2012-10-01 05:06:52 +0000134 "mmc dev ${mmcdev}; if mmc rescan; then " \
Mike Rapoport8abe7302010-12-18 17:43:19 -0500135 "if run loadbootscript; then " \
136 "run bootscript; " \
137 "else " \
138 "if run loaduimage; then " \
139 "run mmcboot; " \
140 "else run nandboot; " \
141 "fi; " \
142 "fi; " \
143 "else run nandboot; fi"
144
Mike Rapoport8abe7302010-12-18 17:43:19 -0500145/*
146 * Miscellaneous configurable options
147 */
Igor Grinbergc73b4f12011-04-18 17:48:28 -0400148#define CONFIG_TIMESTAMP
Nikita Kiryanov0630b032012-01-02 04:01:30 +0000149#define CONFIG_SYS_AUTOLOAD "no"
Mike Rapoport8abe7302010-12-18 17:43:19 -0500150
151#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
152 /* works on */
153#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
154 0x01F00000) /* 31MB */
155
156#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
157 /* load address */
158
159/*
160 * OMAP3 has 12 GP timers, they can be driven by the system clock
161 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
162 * This rate is divided by a local divisor.
163 */
164#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
165#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
Mike Rapoport8abe7302010-12-18 17:43:19 -0500166
167/*-----------------------------------------------------------------------
Mike Rapoport8abe7302010-12-18 17:43:19 -0500168 * Physical Memory Map
169 */
Mike Rapoport8abe7302010-12-18 17:43:19 -0500170#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Mike Rapoport8abe7302010-12-18 17:43:19 -0500171
Mike Rapoport8abe7302010-12-18 17:43:19 -0500172/*-----------------------------------------------------------------------
173 * FLASH and environment organization
174 */
175
176/* **** PISMO SUPPORT *** */
Mike Rapoport8abe7302010-12-18 17:43:19 -0500177/* Monitor at start of flash */
178#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Igor Grinberg315ef7e2012-10-07 01:17:34 +0000179#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
Mike Rapoport8abe7302010-12-18 17:43:19 -0500180
Adam Ford6b1c1652017-09-04 21:08:02 -0500181#define CONFIG_ENV_ADDR 0x260000
Mike Rapoport8abe7302010-12-18 17:43:19 -0500182
Mike Rapoport8abe7302010-12-18 17:43:19 -0500183/* additions for new relocation code, must be added to all boards */
184#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
185#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
186#define CONFIG_SYS_INIT_RAM_SIZE 0x800
187#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
188 CONFIG_SYS_INIT_RAM_SIZE - \
189 GENERATED_GBL_DATA_SIZE)
190
Igor Grinbergd2367bc2011-04-18 17:54:33 -0400191/* Status LED */
Igor Grinberg5ef7b862013-11-06 16:39:47 +0200192#define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
Igor Grinbergd2367bc2011-04-18 17:54:33 -0400193
Nikita Kiryanova6b2b732013-02-24 06:19:23 +0000194#define CONFIG_SPLASHIMAGE_GUARD
195
Nikita Kiryanov2247eb42013-01-30 21:39:58 +0000196/* Display Configuration */
Nikita Kiryanov2247eb42013-01-30 21:39:58 +0000197#define LCD_BPP LCD_COLOR16
198
Nikita Kiryanovc4a295a2012-12-22 21:03:48 +0000199#define CONFIG_SPLASH_SCREEN
Nikita Kiryanov7f9ceea2015-01-14 10:42:54 +0200200#define CONFIG_SPLASH_SOURCE
Nikita Kiryanovc4a295a2012-12-22 21:03:48 +0000201#define CONFIG_BMP_16BPP
Nikita Kiryanov25da1522013-10-16 17:23:29 +0300202#define CONFIG_SCF0403_LCD
203
Stefan Roese8ef10bd2013-12-04 13:54:18 +0100204/* Defines for SPL */
Stefan Roese8ef10bd2013-12-04 13:54:18 +0100205
Paul Kocialkowski341e8cd2014-11-08 23:14:55 +0100206#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
Guillaume GARDET602a16c2014-10-15 17:53:11 +0200207#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Stefan Roese8ef10bd2013-12-04 13:54:18 +0100208
Stefan Roese8ef10bd2013-12-04 13:54:18 +0100209#define CONFIG_SPL_NAND_BASE
210#define CONFIG_SPL_NAND_DRIVERS
211#define CONFIG_SPL_NAND_ECC
Stefan Roese8ef10bd2013-12-04 13:54:18 +0100212
213/* NAND boot config */
214#define CONFIG_SYS_NAND_5_ADDR_CYCLE
215#define CONFIG_SYS_NAND_PAGE_COUNT 64
216#define CONFIG_SYS_NAND_PAGE_SIZE 2048
217#define CONFIG_SYS_NAND_OOBSIZE 64
218#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
219#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
220/*
221 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
222 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
223 */
224#define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
225 10, 11, 12 }
226#define CONFIG_SYS_NAND_ECCSIZE 512
227#define CONFIG_SYS_NAND_ECCBYTES 3
228#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
229
230#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
231#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
232
Tom Rinicfff4aa2016-08-26 13:30:43 -0400233#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
234 CONFIG_SPL_TEXT_BASE)
Stefan Roese8ef10bd2013-12-04 13:54:18 +0100235
236/*
237 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
238 * older x-loader implementations. And move the BSS area so that it
239 * doesn't overlap with TEXT_BASE.
240 */
Stefan Roese8ef10bd2013-12-04 13:54:18 +0100241#define CONFIG_SPL_BSS_START_ADDR 0x80100000
242#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
243
244#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
245#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
246
Nikita Kiryanovd6554782016-04-16 17:55:09 +0300247/* EEPROM */
Nikita Kiryanovd6554782016-04-16 17:55:09 +0300248#define CONFIG_ENV_EEPROM_IS_ON_I2C
249#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
250#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
251#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
252#define CONFIG_SYS_EEPROM_SIZE 256
253
Mike Rapoport8abe7302010-12-18 17:43:19 -0500254#endif /* __CONFIG_H */