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git01.mediatek.com / filogic / uboot / 01bcfc20370db1c3d89d8c6b98a1fbb24eeb1c06 / . / arch / sandbox / dts / sandbox.dts
blob: 16a33db87d3f3d2a2e3c95017b5ba76b7a4282ba [file] [log] [blame]
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]1/dts-v1/;
2
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]3#include <config.h>
4
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]5/ {
Simon Glassfd91fc92014-10-13 23:41:48 -0600[diff] [blame]6 #address-cells = <1>;
Simon Glassf905be82015-03-05 12:25:13 -0700[diff] [blame]7 #size-cells = <1>;
Simon Glass00c34d5b2017-06-15 21:37:53 -0600[diff] [blame]8 model = "sandbox";
Simon Glassfd91fc92014-10-13 23:41:48 -0600[diff] [blame]9
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]10 aliases {
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]11 i2c0 = &i2c_0;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]12 pci0 = &pci;
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]13 rtc0 = &rtc_0;
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]14 axi0 = &axi;
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]15 spi0 = &spi;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]16 };
17
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]18 memory {
19 reg = <0 CONFIG_SYS_SDRAM_SIZE>;
20 };
21
Simon Glass699c9ca2018-10-01 12:22:08 -0600[diff] [blame]22 cros_ec: cros-ec {
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]23 reg = <0 0>;
Simon Glasse5501552018-11-06 15:21:27 -0700[diff] [blame]24 u-boot,dm-pre-reloc;
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]25 compatible = "google,cros-ec-sandbox";
Simon Glass1f6acb52014-02-27 13:25:59 -0700[diff] [blame]26 };
27
Joe Hershberger89590c82018-07-02 14:47:54 -0500[diff] [blame]28 ethrawbus {
29 compatible = "sandbox,eth-raw-bus";
30 skip-localhost = <0>;
31 };
32
Simon Glass45ab0082015-05-22 15:42:16 -0600[diff] [blame]33 eth@10002000 {
34 compatible = "sandbox,eth";
35 reg = <0x10002000 0x1000>;
36 fake-host-hwaddr = [00 00 66 44 22 00];
37 };
38
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]39 i2c_0: i2c@0 {
Simon Glass4f46a592014-12-10 08:55:53 -0700[diff] [blame]40 #address-cells = <1>;
41 #size-cells = <0>;
Simon Glassf905be82015-03-05 12:25:13 -0700[diff] [blame]42 reg = <0 0>;
Simon Glass4f46a592014-12-10 08:55:53 -0700[diff] [blame]43 compatible = "sandbox,i2c";
44 clock-frequency = <400000>;
Masahiro Yamada0b53a752015-08-27 12:44:30 +0900[diff] [blame]45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_i2c0>;
Simon Glassfefc7ba2017-04-10 11:34:51 -0600[diff] [blame]47 };
48
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]49 pci: pci-controller {
50 compatible = "sandbox,pci";
51 device_type = "pci";
52 #address-cells = <3>;
53 #size-cells = <2>;
54 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
55 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]56 };
57
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]58 spi: spi@0 {
Simon Glasse5501552018-11-06 15:21:27 -0700[diff] [blame]59 u-boot,dm-pre-reloc;
Simon Glass45ab0082015-05-22 15:42:16 -0600[diff] [blame]60 #address-cells = <1>;
61 #size-cells = <0>;
62 reg = <0 0>;
63 compatible = "sandbox,spi";
64 cs-gpios = <0>, <&gpio_a 0>;
Joe Hershberger6ab76992015-03-22 17:09:13 -0500[diff] [blame]65 };
Joe Hershberger586cbd12015-03-22 17:09:21 -0500[diff] [blame]66
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]67};
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]68
Simon Glass28db4692019-05-18 11:59:41 -0600[diff] [blame]69#include "sandbox.dtsi"
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]70#include "cros-ec-keyboard.dtsi"
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]71#include "sandbox_pmic.dtsi"