blob: c9f92bc3895dd9baf6ad1493bd3cd6c15d31e851 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Hannes Petermaierf04e9992014-03-06 14:39:06 +01002/*
Hannes Schmelzer2d9a3cd2018-01-09 19:01:32 +01003 * Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at> -
4 * B&R Industrial Automation GmbH - http://www.br-automation.com
Hannes Petermaierf04e9992014-03-06 14:39:06 +01005 */
6
7#ifndef AM335X_FB_H
8#define AM335X_FB_H
9
Dario Binacchi017b4692020-02-22 14:05:45 +010010#if !CONFIG_IS_ENABLED(DM_VIDEO)
11
Dario Binacchi3d9a7132020-02-22 14:05:37 +010012#define HSVS_CONTROL BIT(25) /*
Hannes Petermaierf04e9992014-03-06 14:39:06 +010013 * 0 = lcd_lp and lcd_fp are driven on
14 * opposite edges of pixel clock than
15 * the lcd_pixel_o
16 * 1 = lcd_lp and lcd_fp are driven
17 * according to bit 24 Note that this
18 * bit MUST be set to '0' for Passive
19 * Matrix displays the edge timing is
20 * fixed
21 */
Dario Binacchi3d9a7132020-02-22 14:05:37 +010022#define HSVS_RISEFALL BIT(24) /*
Hannes Petermaierf04e9992014-03-06 14:39:06 +010023 * 0 = lcd_lp and lcd_fp are driven on
24 * the rising edge of pixel clock (bit
25 * 25 must be set to 1)
26 * 1 = lcd_lp and lcd_fp are driven on
27 * the falling edge of pixel clock (bit
28 * 25 must be set to 1)
29 */
Dario Binacchi3d9a7132020-02-22 14:05:37 +010030#define DE_INVERT BIT(23) /*
Hannes Petermaierf04e9992014-03-06 14:39:06 +010031 * 0 = DE is low-active
32 * 1 = DE is high-active
33 */
Dario Binacchi3d9a7132020-02-22 14:05:37 +010034#define PXCLK_INVERT BIT(22) /*
Hannes Petermaierf04e9992014-03-06 14:39:06 +010035 * 0 = pix-clk is high-active
36 * 1 = pic-clk is low-active
37 */
Dario Binacchi3d9a7132020-02-22 14:05:37 +010038#define HSYNC_INVERT BIT(21) /*
Hannes Petermaierf04e9992014-03-06 14:39:06 +010039 * 0 = HSYNC is active high
40 * 1 = HSYNC is avtive low
41 */
Dario Binacchi3d9a7132020-02-22 14:05:37 +010042#define VSYNC_INVERT BIT(20) /*
Hannes Petermaierf04e9992014-03-06 14:39:06 +010043 * 0 = VSYNC is active high
44 * 1 = VSYNC is active low
45 */
46
47struct am335x_lcdpanel {
48 unsigned int hactive; /* Horizontal active area */
49 unsigned int vactive; /* Vertical active area */
50 unsigned int bpp; /* bits per pixel */
51 unsigned int hfp; /* Horizontal front porch */
52 unsigned int hbp; /* Horizontal back porch */
53 unsigned int hsw; /* Horizontal Sync Pulse Width */
54 unsigned int vfp; /* Vertical front porch */
55 unsigned int vbp; /* Vertical back porch */
56 unsigned int vsw; /* Vertical Sync Pulse Width */
Hannes Schmelzer6e1e4282018-01-09 19:01:34 +010057 unsigned int pxl_clk; /* Pixel clock */
Hannes Petermaierf04e9992014-03-06 14:39:06 +010058 unsigned int pol; /* polarity of sync, clock signals */
Hannes Petermaier169aa702015-02-03 13:22:23 +010059 unsigned int pup_delay; /*
60 * time in ms after power on to
61 * initialization of lcd-controller
62 * (VCC ramp up time)
63 */
Hannes Petermaierf04e9992014-03-06 14:39:06 +010064 unsigned int pon_delay; /*
Hannes Petermaier169aa702015-02-03 13:22:23 +010065 * time in ms after initialization of
66 * lcd-controller (pic stabilization)
Hannes Petermaierf04e9992014-03-06 14:39:06 +010067 */
68 void (*panel_power_ctrl)(int); /* fp for power on/off display */
69};
70
71int am335xfb_init(struct am335x_lcdpanel *panel);
72
Dario Binacchi017b4692020-02-22 14:05:45 +010073#endif /* CONFIG_DM_VIDEO */
74
Hannes Petermaierf04e9992014-03-06 14:39:06 +010075#endif /* AM335X_FB_H */