am335x-fb: setup display PLL
The LCDC IP-core an be feed from several clock sources, one of those is
a dedicated DPLL for generating a dividable base-clock for this IP-core.
The TRM specifies the maximum input frequency for the LCCD with 200 MHz,
so we must not exceed this value with the PLL frequency (which can lock
much higher).
This patch tries every combination of multipliers and divisors of the
PLL and the IP-core itself for getting as near as possible the the
requested panel->pxl_clk.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
diff --git a/drivers/video/am335x-fb.h b/drivers/video/am335x-fb.h
index 903a8f1..f99b341 100644
--- a/drivers/video/am335x-fb.h
+++ b/drivers/video/am335x-fb.h
@@ -53,7 +53,7 @@
unsigned int vfp; /* Vertical front porch */
unsigned int vbp; /* Vertical back porch */
unsigned int vsw; /* Vertical Sync Pulse Width */
- unsigned int pxl_clk_div; /* Pixel clock divider*/
+ unsigned int pxl_clk; /* Pixel clock */
unsigned int pol; /* polarity of sync, clock signals */
unsigned int pup_delay; /*
* time in ms after power on to